Ethernet Clock Generator, 10 Clock Outputs
AD9571
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may
result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Fully integrated VCO/PLL core
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filter
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Ethernet line cards, switches, and routers
SCSI, SATA, and PCI-express
PCI support included
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
XTAL
OSC
REFCLK
REFSEL
6 × 25MHz
CMOS
1 × 33.33MHz
2 × 100MHz OR
125MHz
1 × 156.25MHz
FORCE_LOW
CMOS
LVPECL OR
LVDS
VCO
PFD/CP
3RD-ORDER
LPF
FREQSEL
DIVIDERS
AD9571
07499-001
Figure 1.
GENERAL DESCRIPTION
The AD9571 provides a multioutput clock generator function
comprising a dedicated PLL core that is optimized for Ethernet
line card applications. The integer-N PLL design is based on the
Analog Devices, Inc., proven portfolio of high performance, low
jitter frequency synthesizers to maximize network performance.
Other applications with demanding phase noise and jitter
requirements also benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference.
Each output divider and feedback divider ratio is prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame
chip scale package and can be operated from a single 3.3 V
supply. The operating temperature range is 40°C to +8C.
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
48 + 2 SWITCH/MAC
OPTIONAL
CX-4 PHY
CPU
ISLAND
AD9571
XAUI
6 × 25MHz
2 × 125MHz
1 × 156.25MHz
1 × 33.33MHz
07499-002
Figure 2. Typical Application
AD9571* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
AD9571 Evaluation Board
DOCUMENTATION
Data Sheet
AD9571: Ethernet Clock Generator, 10 Clock Outputs
TOOLS AND SIMULATIONS
AD9571/AD9572 IBIS Model
DESIGN RESOURCES
AD9571 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD9571 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD9571
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
PLL Characteristics ...................................................................... 3
LVDS Clock Output Jitter ............................................................ 4
LVPECL Clock Output Jitter ....................................................... 5
CMOS Clock Output Jitter .......................................................... 5
Reference Input ............................................................................. 5
Clock Outputs ............................................................................... 6
Timing Characteristics................................................................. 6
Control Pins .................................................................................. 7
Power .............................................................................................. 7
Crystal Oscillator .......................................................................... 7
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions ............................10
Typical Performance Characteristics ............................................12
Terminology .....................................................................................13
Theory of Operation .......................................................................14
Outputs .........................................................................................14
Phase Frequency Detector (PFD) and Charge Pump.............15
Power Supply ................................................................................15
CMOS Clock Distribution .........................................................15
LVPECL Clock Distribution ......................................................16
LVDS Clock Distribution ...........................................................16
Reference Input............................................................................16
Power and Grounding Considerations and Power Supply
Rejection .......................................................................................16
Outline Dimensions ........................................................................17
Ordering Guide............................................................................17
REVISION HISTORY
8/09—Revision 0: Initial Version

AD9571ACPZPEC-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products 10 Clock Outputs Ethernet
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union