AD9571
Rev. 0 | Page 4 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
PLL Noise (125 MHz LVPECL Output)
@ 1 kHz −121 dBc/Hz 33.33 MHz output disabled
@ 10 kHz −127 dBc/Hz 33.33 MHz output disabled
@ 100 kHz −128 dBc/Hz 33.33 MHz output disabled
@ 1 MHz −148 dBc/Hz 33.33 MHz output disabled
@ 10 MHz −152 dBc/Hz 33.33 MHz output disabled
@ 30 MHz −153 dBc/Hz 33.33 MHz output disabled
PLL Noise (100 MHz LVPECL Output)
@ 1 kHz −115 dBc/Hz 33.33 MHz output disabled
@ 10 kHz −121 dBc/Hz 33.33 MHz output disabled
@ 100 kHz −128 dBc/Hz 33.33 MHz output disabled
@ 1 MHz −148 dBc/Hz 33.33 MHz output disabled
@ 10 MHz −150 dBc/Hz 33.33 MHz output disabled
@ 30 MHz −150 dBc/Hz 33.33 MHz output disabled
Phase Noise (33.33 MHz CMOS Output)
@ 1 kHz −131 dBc/Hz
@ 10 kHz −138 dBc/Hz
@ 100 kHz −139 dBc/Hz
@ 1 MHz −151 dBc/Hz
@ 5 MHz −152 dBc/Hz
Phase Noise (25 MHz CMOS Output)
@ 1 kHz −133 dBc/Hz
@ 10 kHz −143 dBc/Hz
@ 100 kHz −147 dBc/Hz
@ 1 MHz −148 dBc/Hz
@ 5 MHz −148 dBc/Hz
Spurious Content
1
−70 dBc Dominant amplitude with all outputs active
PLL Figures of Merit −217.5 dBc/Hz
1
When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content may be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ) 100 MHz
125 MHz
1
,
33.33 MHz = Off/On 156.25 MHz Unit Test Conditions/Comments
12 kHz to 20 MHz 0.50 0.41/0.77 0.41 ps rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
1.875 MHz to 20 MHz 0.17 ps rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
200 kHz to 10 MHz 0.30 0.24/0.66 ps rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
1
The typical 125 MHz rms jitter data collected from the differential pair of Pin 21 and Pin 22, unless otherwise noted.
