AD9571
Rev. 0 | Page 12 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Both 100 MHz and 125 MHz outputs enabled; 33.33 MHz output disabled.
–100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07499-007
Figure 7. 125 MHz Phase Noise
–100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07499-008
Figure 8. 25 MHz Phase Noise
–100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07499-009
Figure 9. 156.25 MHz Phase Noise
–100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07499-010
Figure 10. 100 MHz Phase Noise
AD9571
Rev. 0 | Page 13 of 20
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to 360
degrees for each cycle. Actual signals, however, display a certain
amount of variation from ideal phase progression over time.
This phenomenon is called phase jitter. Although many causes
can contribute to phase jitter, one major cause is random noise,
which is characterized statistically as gaussian (normal) in
distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
Phase Noise
When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset
interval, and it can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Because these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the gaussian distribution.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable
to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources has been subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
AD9571
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
XTAL
OSC
REFCLK
REFSEL
VS
GND
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 25
DIVIDE
BY 4
DIVIDE
BY 4
DIVIDE
BY 5
DIVIDE
BY 4
DIVIDE
BY 5
DIVIDE
BY 3
25M
CMOS
25MHz
25M
25M
CMOS
25M
25M
CMOS
25M
33M
33.33MHz
CMOS
1
0
V
LDO
VCO
0
1
1
0
125MHz/
100MHz
LVPECL/
LVDS
100M/125M
100M/125M
125MHz/
100MHz
LVPECL/
LVDS
100M/125M
100M/125M
156.25MHz
LVPECL/
LVDS
156M
156M
FREQSEL
AD9571
LEVEL
DECODE
FORCE_LOW
07499-011
Figure 11. Detailed Block Diagram
Figure 11 shows a block diagram of the AD9571. The chip
consists of a PLL core, which is configured to generate the
specific clock frequencies required for Ethernet applications,
without any user programming. This PLL is based on proven
Analog Devices synthesizer technology, noted for its exceptional
phase noise performance. The AD9571 is highly integrated and
includes loop filters, regulators for supply noise immunity, all
the necessary dividers with multiple output buffers in a choice
of formats, and a crystal oscillator. A user need only supply a
25 MHz reference clock or an external crystal to implement an
entire line card clocking solution that does not require any
processor intervention. Six copies of the 25 MHz reference
source are also available.
OUTPUTS
Table 14 provides a summary of the outputs available.
Table 14. Output Formats
Frequency Format Copies
25 MHz CMOS 6
156.25 MHz LVPECL/LVDS 1
100 MHz or 125 MHz LVPECL/LVDS 2
33.33 MHz CMOS 1
Note that the pins labeled 100M/125M can provide 100 MHz or
125 MHz by strapping the FREQSEL pin as shown in Table 15.

AD9571ACPZPEC-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products 10 Clock Outputs Ethernet
Lifecycle:
New from this manufacturer.
Delivery:
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