AD9571
Rev. 0 | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. * = SHORT TO PIN 36.
2. ** = SHORT TO PIN 14.
3. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO
FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
PIN 1
INDICATOR
1GND
2VS
325M
425M
5VS
6XO
7XO
8REFCLK
9REFSEL
10GND
23 33M
24 VS
25 VS
26 VS
27 FREQSEL
28 VS
29 25M
30 25M
22 100M/125M
21
100M/125M
11VS
12**
13**
15VS
17156M
16VS
18156M
19100M/125M
20100M/125M
14BYPASS2
33
VS
34
GND
35
VS
36
BYPASS1
37
FORCE_LOW
38
*
39
VS
40
VS
32
25M
31
25M
TOP VIEW
(Not to Scale)
AD9571
LVPECL/
LVDS
07499-006
Figure 6. Pin Configuration
Table 13. Pin Function Descriptions
1
Pin No. Mnemonic Description
2 VS Power Supply Connection for the 25M CMOS Buffer.
3, 4, 29, 30, 31, 32 25M CMOS 25 MHz Output.
5 VS Power Supply Connection for the Crystal Oscillator.
6, 7 XO External 25 MHz Crystal.
8 REFCLK 25 MHz Reference Clock Input. Tie low when not in use.
9 REFSEL Logic Input. Used to select the reference source.
11 VS Power Supply Connection for the GbE PLL.
1, 10, 34 GND Ground Pins. The external paddle must be attached to GND.
14, 36 BYPASS2, BYPASS1 These pins are for bypassing each LDO to ground with a 220 nF capacitor.
15 VS Power Supply Connection for the GbE VCO.
16 VS Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers.
17 156M LVPECL/LVDS Output at 156.25 MHz.
18
156M
Complementary LVPECL/LVDS Output at 156.25 MHz.
19, 21 100M/125M LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping.
20, 22
100M
/ Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.
125M
23 33M CMOS 33.33 MHz Output.
24 VS Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers.
25 VS Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers.
26 VS Power Supply Connection for the GbE PLL Feedback Divider.
27 FREQSEL Logic Input. Used to configure output drivers.
28 VS Power Supply Connection for the FC PLL Feedback Divider.
