LTC3774
13
3774fc
For more information www.linear.com/LTC3774
OPERATION
Multiphase Operation
For output loads that demand high current, multiple
LTC3774s can be daisychained to run out of phase to provide
more output current without increasing input and output
voltage ripple. The MODE/PLLIN pin allows the LTC3774 to
synchronize to the CLKOUT signal of another LTC3774. The
CLKOUT signal can be connected to the MODE/PLLIN pin of
the following LTC3774 stage to line up both the frequency
and the phase of the entire system. Tying the PHSMD pin to
INTV
CC
, GND or floating it generates a phase difference
(between CH1 and CLKOUT) of 240°, 60° or 90° respec-
tively, and a phase difference (between CH1 and CH2) of
120
°,
180° or 180°. Tying PHSMD to 1/4 or 3/4 of INTV
CC
generates a phase difference of 60° and 45° between CH1
and CLKOUT. Figure 1 shows the PHSMD connections
necessary for 3-, 4-, 6-, 8- or 12-phase operation. A total
of 12 phases can be daisychained to run simultaneously
out of phase with respect to each other.
Sensing the Output Voltage with a
Differential Amplifier
The LTC3774
includes a low offset, high input impedance,
unity-gain, high bandwidth differential amplifier for ap
-
plications that require true remote sensing. Sensing the
load across the load capacitors directly benefits regulation
in high current, low voltage applications, where board
interconnection losses can be a significant portion of the
total error budget. Connect V
OSNS
+
to the center tap of the
feedback divider across the output load, and V
OSNS
to
the load ground. See Figure 2.
The LTC3774 differential amplifier is configured for unity
gain, meaning that the difference between V
OSNS
+
and
V
OSNS
is translated to its output, relative to GND. The
differential amplifiers output is internally connected to
the error amplifier inverting input.
Care should be taken to route the V
OSNS
+
and V
OSNS
PCB
traces parallel to each other all the way to the remote sens-
ing points on the board. In addition, avoid routing these
sensitive traces near any high speed switching nodes in
the cir
cuit
. Ideally, the V
OSNS
+
and V
OSNS
traces should
be shielded by a low impedance ground plane to maintain
signal integrity.
Figure 2. Differential Amplifier Connection
LTC3774
FEEDBACK DIVIDER
V
OSNS
+
C
F1
R
D1
C
OUT1
C
OUT2
V
OUT
10Ω
R
D2
V
OSNS
3774 F02
10Ω
+
DIFFAMP
LTC3774
14
3774fc
For more information www.linear.com/LTC3774
OPERATION
Power Good (PGOOD Pin)
The PGOOD pin is connected to the open drain of an inter-
nal N-channel MOSFET. The MOSFET turns on and pulls
the PGOOD pin low when the V
OSNS
+
pin voltage is not
within ±7.5% of the 0.6V reference voltage. The PGOOD
pin is also pulled low when the RUN pin is below 1.14V
or when the LTC3774 is in the soft-start or tracking up
phase. When the V
OSNS
+
pin voltage is within the ±7.5%
regulation window, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source of up to 6V. The PGOOD pin will flag power good
immediately when the V
OSNS
+
pin is within the regulation
window. However, there is an internal 45µs power-bad
mask when the V
OSNS
+
goes out of the window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi
-
tions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the over
voltage condition is cleared.
Undervoltage Lockout
The LTC3774 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTV
CC
voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV
CC
is below
3.75V. To prevent oscillation when there is a disturbance
on the INTV
CC
, the UVLO comparator has 500mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the V
IN
supply. Because the RUN pin has a preci-
sion turn-on reference of 1.22V, one can use a resistor
divider to V
IN
to turn on the IC when V
IN
is high enough.
An extra 4µA of current flows out of the RUN pin once the
RUN pin voltage passes 1.22V. The RUN comparator itself
has about 80mV of hysteresis. One can program additional
hysteresis for the RUN comparator by adjusting the values
of the resistive divider. For accurate V
IN
undervoltage
detection, V
IN
needs to be higher than 4.75V. Always
set the V
IN
undervoltage detection threshold higher than
the power stage UVLO threshold so that the LTC3774 is
enabled after the power stage is.
LTC3774
15
3774fc
For more information www.linear.com/LTC3774
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3774 application circuit. The LTC3774 is
designed and optimized for use with a very low DCR
value by utilizing a novel approach to reduce the noise
sensitivity of the sensing signal by a factor of 14dB. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, as the
DCR value drops below 1mΩ, the signal-to-noise ratio
is low and current sensing is difficult. LTC3774 uses an
LTC proprietary technique to solve this issue. In general,
external component selection is driven by the load require
-
ment, and begins with the DCR and inductor value. Next,
power MOSFETs are selected. Finally, input and output
capacitors are selected.
Current Limit Programming
The ILIM pin is a 5-level logic input which sets the maxi
-
mum current limit of the controller. When ILIM is either
grounded
,
floated or tied to INTV
CC
, the typical value for
the maximum current sense threshold will be 10mV,
20mV or 30mV, respectively. Setting ILIM to one-fourth
INTV
CC
and three-fourths INTV
CC
for maximum current
sense thresholds of 15mV and 25mV. Setting I
LIM
using
a resistor divider off of INTV
CC
will allow the maximum
current sense threshold setting to not change when the
5.5V LDO is in dropout at start-up. Please note that the
I
LIM
pin has an internal 500k pull-down to GND and a 500k
pull-up to INTV
CC
.
Which setting should be used? For the best current limit
accuracy, use the highest setting that is applicable to the
output requirements.
SNSD
+
, SNSA
+
and SNS
Pins
The SNSA
+
and SNS
pins are the inputs to the current
comparators, while the SNSD
+
pin is the input of an
internal amplifier. The operating input voltage range is
0V to 3.5V for all three sense pins. All the positive sense
pins that are connected to the current comparator or the
amplifier are high impedance with input bias currents
of less than 1µA, but there is also a resistance of about
300k from the SNS
pin to ground. The SNS
should
be connected directly to V
OUT
. The SNSD
+
pin connects
to the filter that has a R1C1 time constant matched to
L/DCR of the inductor. The SNSA
+
pin is connected to
the second filter with the time constant one-fifth that
of R1C1. Care must be taken not to float these pins
during normal operation. Filter components, especially
capacitors, must be placed close to the LTC3774, and
the sense lines should run close together to a Kelvin con
-
nection underneath the current sense element (Figure3).
Because the LTC3774 is designed to be used with a very
low DCR value to sense inductor current, without proper
care, the parasitic resistance, capacitance and inductance
will degrade the current sense signal integrity, making
the programmed current limit unpredictable. As shown
in Figure 4, resistors R1 and R2 are placed close to the
output inductor and capacitors C1 and C2 are close to
the IC pins to prevent noise coupling to the sense signal.
Figure 3. Sense Lines Placement with Inductor DCR
C
OUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR
3774 F03

LTC3774EUHE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing
Lifecycle:
New from this manufacturer.
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