LTC3774
20
3774fc
For more information www.linear.com/LTC3774
APPLICATIONS INFORMATION
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTC3774 can safely power up into a
pre-biased output without discharging it.
The LTC3774 accomplishes this by disabling both the top
and bottom MOSFETs until the TK/SS pin voltage and the
internal soft-start voltage are above the V
OSNS
+
pin volt-
age. When V
OSNS
+
is higher than TK/SS or the internal
soft-start voltage, the error amp output is railed low. The
control loop would like to turn the bottom MOSFET on,
which would discharge the output. Disabling both top and
bottom MOSFETs prevents the pre-biased output voltage
from being discharged. When TK/SS and the internal
soft-start both cross 500mV or V
OSNS
+
, whichever is
lower, both top and bottom MOSFETs are enabled. If the
pre-bias is higher than the OV threshold, the bottom gate
is turned on immediately to pull the output back into the
regulation window.
Overcurrent Fault Recovery
When the output of the power supply is loaded beyond its
preset current limit, the regulated output voltage will col
-
lapse depending on the load. The output may be shorted
to ground through a ver
y low impedance path or it may
be a resistive short
, in which case the output will collapse
partially, until the load current equals the preset current
limit. The controller will continue to source current into
the short. The amount of current sourced depends on
the ILIM pin setting and the V
OSNS
+
voltage as shown in
the Current Foldback graph in the Typical Performance
Characteristics section.
Upon removal of the short, the output soft starts using
the internal soft-start, thus reducing output overshoot. In
the absence of this feature, the output capacitors would
have been charged at current limit, and in applications
with minimal output capacitance this may have resulted
in output overshoot. Current limit foldback is not disabled
during an overcurrent recovery. The load must step below
the folded back current limit threshold in order to restart
from a hard short.
Phase Shedding/n+1 Redundancy (HIZB Pin)
Unlike the RUN pins, the HIZB pins cause the PWM to enter
its high impedance state while not pulling down on ITH or
TK/SS. This allows two possibilities: First, one can shed a
phase based on load requirements via the HIZB pin. This im
-
proves low current efficiency in a single output multiphase
case by reducing switching losses. Second, for applications
that require n+1 redundancy, it is now easy to disconnect
a channel with damaged MOSFETs or drivers. When com
-
bined with a Hot Swap™ controller, such as the LTC4226,
the HIZB pin could be connected to the gate of the Hot
Swap switch.
When a damaged MOSFET triggers the Hot
Swap controller, it also disables the corresponding chan
-
nel’s power stage, disconnecting it. Since ITH and TK/SS
are unaffected, it does not affect the rest of the system.
The propagation delay from HIZB falling to high impedance
on P
WM is <200ns.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, f
OSC
, directly determine
the inductor’s peak-to-peak ripple current:
I
RIPPLE
=
V
OUT
V
IN
V
IN
– V
OUT
f
OSC
•L
⎛
⎝
⎜
⎞
⎠
⎟
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L ≥
IN
OUT
f
•I
•
OUT
V
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
