LTC3774EUHE#TRPBF Datasheet LTC3774EUHE#PBF, LTC3774IUHE#PBF, LTC3774EUHE#TRPBF | P28-P30

LTC3774

3774fc

For more information www.linear.com/LTC3774

The minimum on-time for the LTC3774 is approximately

90ns, with good PCB layout, minimum 30% inductor

current ripple and at least 2mV ripple on the current

sense signal. The minimum on-time can be affected by

PCB switching noise in the voltage and current loop.

As the peak sense voltage decreases the minimum on-

time gradually increases This is of particular concern in

for

ced continuous applications with low ripple current at

light loads

. If the duty cycle drops below the minimum

on-time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent

age of input power.

Although all

dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3774 circuits: 1) IC V

current, 2) MOSFET

driver current, 3) I

R losses, 4) topside MOSFET transi-

tion losses.

The V

current is the DC supply current given in the

Electrical Characteristics table. V

current typically

results in a small (<0.1%) loss.

The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time

a MOSFET gate is switched from low to high to low

again, a packet of charge dQ moves from the driver

supply to ground. The resulting dQ/dt is a current

out of the driver supply that is typically much larger

than the control circuit current. In continuous mode,

GATECHG

= f(Q

+ Q

), where Q

and Q

are the gate

charges of the topside and bottom side MOSFETs.

APPLICATIONS INFORMATION

3. I

R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor and current sense re-

sistor. In continuous mode, the average output current

flows through L and R

SENSE

, but is chopped between

the topside MOSFET and the synchronous MOSFET.

If the two MOSFETs have approximately the same

DS(ON)

, then the resistance of one MOSFET can simply

be summed with the resistances of L and R

SENSE

obtain I

R losses. For example, if each R

DS(ON)

= 10mΩ,

= 10mΩ, R

SENSE

= 5mΩ, then the total resistance is

25mΩ. This results in losses ranging from 2% to 8%

as the output current increases from 3A to 15A for a 5V

output, or a 3% to 12% loss for a 3.3V output.

Efficiency varies as the inverse square of V

OUT

for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Transition Loss = (1.7) V

• I

O(MAX)

• C

RSS

• f

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

has adequate charge storage and very low ESR at

the switching frequency. A 25W supply will typically

require a minimum of 20µF to 40µF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. Other

losses including Schottky conduction losses during

dead time and inductor core losses generally account

for less than 2% total additional loss.

LTC3774

3774fc

For more information www.linear.com/LTC3774

APPLICATIONS INFORMATION

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

OUT

shifts by an

amount equal to ∆I

LOAD

•

ESR, where ESR is the effective

series resistance of C

OUT

. ∆I

LOAD

also begins to charge or

discharge C

OUT

generating the feedback error signal that

forces the regulator to adapt to the current change and

return V

OUT

to its steady-state value. During this recovery

time V

OUT

can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I

pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The I

external components shown

in the Typical Application circuit will provide an adequate

starting point for most applications. The I

series R

-C

filter sets the dominant pole-zero loop compensation.

The values can be modified slightly (from 0.5 to 2 times

their suggested values) to optimize transient response

once the final PC layout is done and the particular output

capacitor type and value have been determined. The output

capacitors need to be selected because the various types

and values determine the loop gain and phase. An output

current pulse of 20% to 80% of full-load current having a

rise time of 1µs to 10µs will produce output voltage and

pin waveforms that will give a sense of the overall

loop stability without breaking the feedback loop. Placing

a power MOSFET directly across the output capacitor and

driving the gate with an appropriate signal generator is a

practical way to produce a realistic load step condition. The

initial output voltage step resulting from the step change

in output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

phase margin. This is why it is better to look at the I

pin signal which is in the feedback loop and is the filtered

and compensated control loop response. The gain of the

loop will be increased by increasing R

and the bandwidth

of the loop will be increased by decreasing C

. If R

increased by the same factor that C

is decreased, the

zero frequency will be kept the same, thereby keeping the

phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and

will demonstrate the actual overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

LOAD

to C

OUT

is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • C

LOAD

. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

IC. These items are also illustrated graphically in the layout

diagram of Figure 14. Check the following in the PC layout:

1. The INTV

decoupling capacitor should be placed

immediately adjacent to the IC between the INTV

and GND plane. A 1µF ceramic capacitor of the X7R or

X5R type is small enough to fit very close to the IC. An

additional 4.7µF to 10µF of ceramic, tantalum or other

very low ESR capacitance is recommended in order to

keep the internal IC supply quiet.

LTC3774

3774fc

For more information www.linear.com/LTC3774

2. Place the feedback divider between the + and – terminals

of COUT. Route V

OSNS

and V

OSNS

–

with minimum PC

trace spacing from the IC to the feedback divider.

3. Are the SNSA

, SNSD

and SNS

–

printed circuit traces

routed together with minimum PC trace spacing? The

filter capacitors between SNSA

, SNSD

and SNS

–

should be as close as possible to the pins of the IC.

4. Do the (+) plates of C

connect to the drain of the

topside MOSFET as closely as possible? This capacitor

provides the pulsed current to the MOSFET.

5. Keep the switching nodes away from sensitive small-

signal nodes (SNSD

, SNSA

, SNS

–

, V

OSNS

, V

OSNS

–

Ideally the PWM and switch nodes printed circuit traces

should be routed away and separated from the IC and

especially the quiet side of the IC. Separate the high dv/

dt traces from sensitive small-signal nodes with ground

traces or ground planes.

6. Use a low impedance source such as a logic gate to

drive the MODE/PLLIN pin and keep the lead as short

as possible.

7. The 47pF to 330pF ceramic capacitor between the I

pin and signal ground should be placed as close as

possible to the IC. Figure 14 illustrates all branch cur

rents in a switching regulator. It becomes very clear

after studying the current waveforms why it is critical to

keep the high switching current paths to a small physical

size. High electric and magnetic fields will radiate from

these loops just as radio stations transmit signals. The

output capacitor ground should return to the negative

terminal of the input capacitor and not share a com

mon ground path with any switched current paths. The

left half of the circuit gives rise to the

noise generated

by a switching regulator. The ground terminations of

the synchronous MOSFET and Schottky diode should

return to the bottom plate(s) of the input capacitor(s)

with a short isolated PC trace since very high switched

currents are present. External OPTI-LOOP

compensa-

tion allows overcompensation for PC layouts which are

not optimized but this is not the recommended design

procedure.

APPLICATIONS INFORMATION

Figure 14. Branch Current Waveforms

OUT

SW2

SW1

SENSE

3774 F14

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

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LTC3774EUHE#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing

Lifecycle:

New from this manufacturer.

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LTC3774EUHE#TRPBF

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