19
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK
and the rising edge of RCLK is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode:
D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
REN
4294 drw 23
t
ENS
t
ENH
t
ENS
D - (m + 1) Words in
FIFO
D - m Words in FIFO
t
PAFS
D - (m + 1) Words
in FIFO
t
PAFS
t
SKEW2
(3)
t
PAFS
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
REN
4294 drw 22
t
ENS
t
ENH
t
ENS
n words in FIFO
(2)
,
n + 1words in FIFO
(3)
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
SKEW2
t
PAES
n Words in FIFO
(2)
,
n + 1 words in FIFO
(3)
(4)
t
PAES
20
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 25. Write Cycle Timing with Double Register-Buffered
FFFF
FFFF
FF
(IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
WCLK
D
0
-
D
17
WEN
FF
RCLK
REN
t
DS
t
WFF
t
WFF
DATA IN VALID
NO OPERATION
(1)
t
SKEW1
4294 drw 25
t
ENS
t
DH
t
ENH
1
2
t
CLKH
t
CLKL
t
CLK
D
0
- D
17
WEN
RCLK
FF
REN
tENH
tENH
Q
0
- Q
17
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
tSKEW1
DATA WRITE
4294 drw 24
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tWFF
tWFF
tA
tENS tENS
tSKEW1
tDS
tA
Wd
(1) (1)
21
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 27.
OROR
OROR
OR
Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered
EFEF
EFEF
EF
(IDT Standard Timing)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and
the rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
W1 W2
W4 W[n +2]
W[n+3]
WCLK
WEN
D
0 - D17
RCLK
tDH
tDS
tENS
tSKEW1
REN
Q0 - Q17
tDS
tA
tREF
OR
W1
DATA IN OUTPUT REGISTER
(1)
W3
1
2
3
tENH
tREF
4294 drw 27
NO OPERATION
RCLK
REN
EF
t
CLKL
t
ENH
t
REF
LAST WORD
t
A
t
OLZ
t
OE
Q
0
-
Q
17
OE
WCLK
WEN
4294 drw 26
D
0
-
D
17
t
ENS
t
ENS
t
ENH
t
DS
t
DH
FIRST WORD
t
OHZ
t
CLK
12
t
REF
t
SKEW1
t
CLKH
(1)

72V215L10TFG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 512x18 3.3V SYNC FIFO
Lifecycle:
New from this manufacturer.
Delivery:
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