72V215L10TFG Datasheet 72V215L10TFG, 72V245L10PFG, 72V205L15PFGI | P22-P24

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

OPERATING CONFIGURATIONS

SINGLE DEVICE CONFIGURATION

A single IDT

72V205/72V215/72V225/72V235/72V245 may be used when

the application requirements are for 256/512/1,024/2,048/4,096 words or less.

These FIFOs are in a single Device Configuration when the First Load (FL),

Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are

configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or

(1,1,0) during reset (Figure 28).

Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO

NOTE:

1. Do not connect any output control signals directly together.

Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36

Synchronous FIFO Memory Used in a Width Expansion Configuration

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control

signals of multiple devices. Status flags can be detected from any one device.

The exceptions are the Empty Flag/Output Ready and Full Flag/Input Ready.

Because of variations in skew between RCLK and WCLK, it is possible for flag

assertion and deassertion to vary by one cycle between FIFOs. To avoid

problems the user must create composite flags by gating the Empty Flags/Output

Ready of every FIFO, and separately gating all Full Flags/Input Ready. Figure

29 demonstrates a 36-word width by using two IDT72V205/72V215/72V225/

72V235/72V245s. Any word width can be attained by adding additional

IDT72V205/72V215/72V225/72V235/72V245s. These FIFOs are in a single

Device Configuration when the First Load (FL), Write Expansion In (WXI) and

Read Expansion In (RXI) control inputs are configured as (FL, RXI,

WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure

29). Please see the Application Note AN-83.

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

READ CLOCK (RCLK)

READ ENABLE (REN)

LOAD (LD)

OUTPUT ENABLE (OE)

DATA IN (D)

DATA OUT (Q)

FULL FLAG/INPUT

READY (FF/IR)

PROGRAMMABLE (PAE)

HALF FULL FLAG (HF)

EMPTY FLAG/OUTPUT

READY (EF/OR)

PROGRAMMABLE (PAF)

RESET (RS)

72V205

72V215

72V225

72V235

72V245

72V205

72V215

72V225

72V235

72V245

RESET (RS)

18 18

FF/IR EF/OR

4294 drw 29

FL WXI RXI

FF/IR EF/OR

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

READ CLOCK (RCLK)

READ ENABLE (REN)

LOAD (LD) OUTPUT ENABLE (OE)

DATA IN (D

- D

)

DATA OUT (Q

- Q

)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE (PAE)

HALF-FULL FLAG (HF)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE (PAF)

RESET (RS)

IDT

72V205

72V215

72V225

72V235

72V245

4294 drw 28

FL RXI WXI

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous

FIFO Memory With Programmable Flags used in Depth Expansion Configuration

LOAD

WRITE CLOCK

WRITE ENABLE

READ CLOCK

READ ENABLE

OUTPUT ENABLE

DATA IN

DATA OUT

RESET

IDT

72V205

72V215

72V225

72V235

72V245

WXO

WXI

RXO

RXI

FIRST LOAD (FL)

Vcc

WXO

WXI

RXO

RXI

WXO

WXI

RXO

RXI

IDT

72V205

72V215

72V225

72V235

72V245

IDT

72V205

72V215

72V225

72V235

72V245

FF/IR

PAF

EF/OR

PAE

FF/IR

PAF

EF/OR

PAE

FF/IR

PAF

EF/OR

PAE

EF/OR

PAE

FF/IR

PAF

4294 drw 30

RCLK

REN

WCLK

WEN

RCLK

REN

WCLK

WEN

RCLK

REN

WCLK

WEN

DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE

(WITH PROGRAMMABLE FLAGS)

These devices can easily be adapted to applications requiring more than

256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth

Expansion using three IDT72V205/72V215/72V225/72V235/72V245s.

Maximum depth is limited only by signal loading.

Follow these steps:

1. The first device must be designated by grounding the First Load (FL)

control input.

2. All other devices must have FL in the HIGH state.

3. The Write Expansion Out (WXO) pin of each device must be tied to

the Write Expansion In (WXI) pin of the next device. See Figure 30.

4.The Read Expansion Out (RXO) pin of each device must be tied to the

Read Expansion In (RXI) pin of the next device. See Figure 30.

5.All Load (LD) pins are tied together.

6.The Half-Full Flag (HF) is not available in this Depth Expansion

Configuration.

7. EF, FF, PAE, and PAF are created with composite flags by ORing

together every respective flags for monitoring. The composite PAE

and PAF flags are not precise.

8. In Daisy Chain mode, the flag outputs are single register-buffered and

the partial flags are in asynchronous timing mode.

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18

Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration

INPUT READY

WRITE ENABLE

WRITE CLOCK

WEN

WCLK

DATA IN

RCLK

READ CLOCK

RCLK

REN

OUTPUT ENABLE

OUTPUT READY

GND

WEN

WCLK

REN

READ ENABLE

DATA OUT

TRANSFER CLOCK

4294 drw 31

n n

RXI

72V205

72V215

72V225

72V235

72V245

WXI

GND

(0,1)

72V205

72V215

72V225

72V235

72V245

RXI

WXI

GND

(0,1)

PAF

PAE

DEPTH EXPANSION CONFIGURATION (FWFT MODE)

In FWFT mode, the FIFOs can be connected in series (the data outputs of

one FIFO connected to the data inputs of the next) with no external logic

necessary. The resulting configuration provides a total depth equivalent to the

sum of the depths associated with each single FIFO. Figure 31 shows a depth

expansion using two IDT72V205/72V215/72V225/72V235/72V245 devices.

Care should be taken to select FWFT mode during Master Reset for all FIFOs

in the depth expansion configuration. The first word written to an empty

configuration will pass from one FIFO to the next (“ripple down”) until it finally

appears at the outputs of the last FIFO in the chain–no read operation is

necessary but the RCLK of each FIFO must be free-running. Each time the data

word appears at the outputs of one FIFO, that device’s OR line goes LOW,

enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for OR of

the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO’s

outputs) after a word has been written to the first FIFO is the sum of the delays

for each individual FIFO:

(N – 1)*(4*transfer clock) + 3*TRCLK

where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.

Note that extra cycles should be added for the possibility that the tSKEW1

specification is not met between WCLK and transfer clock, or RCLK and transfer

clock, for the OR flag.

The “ripple down” delay is only noticeable for the first word written to an empty

depth expansion configuration. There will be no delay evident for subsequent

words written to the configuration.

The first free location created by reading from a full depth expansion

configuration will “bubble up” from the last FIFO to the previous one until it finally

moves into the first FIFO of the chain. Each time a free location is created in one

FIFO of the chain, that FIFO’s IR line goes LOW, enabling the preceding FIFO

to write a word to fill it.

For a full expansion configuration, the amount of time it takes for IR of the first

FIFO in the chain to go LOW after a word has been read from the last FIFO is

the sum of the delays for each individual FIFO:

(N – 1)*(3*transfer clock) + 2 T

WCLK

where N is the number of FIFOs in the expansion and TWCLK is the WCLK

period. Note that extra cycles should be added for the possibility that the t

SKEW1

specification is not met between RCLK and transfer clock, or WCLK and transfer

clock, for the IR flag.

The Transfer Clock line should be tied to either WCLK or RCLK, whichever

is faster. Both these actions result in data moving, as quickly as possible, to the

end of the chain and free locations to the beginning of the chain.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

72V215L10TFG

Mfr. #:

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Description:

FIFO 512x18 3.3V SYNC FIFO

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72V215L10TFG

72V215L10TFG

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