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9LPRS436CKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
IDT
®
Low Power Clock for Intel Atom
®
-Based Systems 1561C — 08/24/11
9LPRS436C
Low Power Clock for Intel Atom
®
-Based Systems
7
CPU Power Management Table
1 Enable
1
X Running Running
1 Enable
0
XHighLow
0
Enable X X Low Low
X
Disable
XXLowLow
CPU(1:0)/ITP CPU#(1:0)/ITPCPU_STOP#
PCI&PCIEX_
STOP#
WOL_STOP#
SMBus
Register OE
Differential Power Management Table
PCIEX/SATA PCIEX/SATA# PCIEX/SATA PCIEX/SATA#
1 Enable X
1
Running Running Running Running Running Running
1 Enable X
0
High Low Running Running Running Running
0
Enable X X Low Low Low /20K Low Low /20K Low
X
Disable
X X Low Low Low /20K Low Low /20K Low
DOT#DOT
Free-Run
CPU_STOP#
PCI&PCIEX_
STOP#
PCI Stoppable
WOL_STOP#
SMBus
Re gis te r OE
Singled-ended Power Management Table
PCIF/PCI PCIF/PCI 25MHz 25MHz
Free-run Stoppable Free-run Stoppable
1 Enable X
1
Running Running Running Running Running Running
1 Enable X
0
Running Low Running Running Running Running
0
Enable X X Low Low Low Low Running Low
X
Disable
X X Low Low Low Low Low Low
12/48MHz
12.288MHz
REFWOL_STOP# CPU_STOP#
PCI&PCIEX_
STOP#
SMBus
Re gis te r OE
PEREQ# Control Table:
10, SATA/PCIe3
2 SATA/PCIe3, 1
31, 2
PEREQ#
PCIe
controlled
Table 2: Slew Rate Selection Table
Bit 1 Bit 0
Slew
Rate
00
Hi-Z
01
0.6X
(1.2V/ns)
10
0.8X
(1.6V/ns)
11
1X
(2.0V/ns)
IDT
®
Low Power Clock for Intel Atom
®
-Based Systems 1561C — 08/24/11
9LPRS436C
Low Power Clock for Intel Atom
®
-Based Systems
8
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V
1,2
3.3V Logic Supply Voltage VDD 4.6 V
1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus int erface V
DD
+0.5 V V
1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C1
Case Temperature Tcase 115 °C
1
Input ESD protectio n ESD prot Human Body Model 2000 V
1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro duc tio n.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
T
amb C
Stand ard Device 0 85 °C
T
am b
I
Industrial Temperature R ange Device -40 85 °C
Su
pp
l
y
Volta
g
eVDDxxx Su
pp
l
y
Volta
g
e 3.135 3.465
V
Input High Voltage V
IHSE
Single-ended 3.3V inputs 2 V
DD
+ 0 .3 V 7
Input Low Voltage V
ILSE
Single-ended 3.3V inputs V
SS
- 0.3 0.8 V 7
FS(4:3 ) Input High Voltage
V
IH_FS4
Single-ended 3.3V FS(4:3) I nputs 2 VDD + 0.3 V
FS(4:3) Input Low Voltage
V
IL_ FS4
Single-ended 3.3V FS(4:3) I nputs
V
SS
- 0.3
0.8 V
Low Threshold Input-
Hi
g
h Volta
g
e
V
IH_FS
3.3 V +/-5% 0.7 VDD+0.3 V
Low Threshold Input-
Low Volta
g
e
V
IL _FS
3.3 V +/-5% V
SS
- 0.3 0.35 V
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 6
Input Leakage Current
I
INRES
Inputs with pull up or pull down resistors
V
IN
= V
DD ,
V
IN
=
GND
-200 200 uA
Output High Voltage V
OHSE
Single-ended outputs, I
OH
= -1mA 2.4 V 5
Output Low Voltage V
OLSE
Single-ended outp uts, I
OL
= 1 mA 0.4 V 5
I
DDVD D3.3
Full Active, C
L
= Full load; IDD 3.3V
106 115 mA
I
D DVD DS USP3 .3
Full Active, C
L
= Full load ; IDD 3.3V 12 15 mA
I
DDPDVDD3.3
3.3V Main Rail 0 mA
I
DDPDSUSP3.3w
VDD_SUSP Rail. 25MHz Running (WOL) 12 15 mA
I
DDPDSUSP3.3
VDD_SUSP Rail. 25MHz Off 3 4 mA
Input Frequency
F
i
V
DD
= 3.3 V
27 MHz 8
Pin Inductance L
pin
7nH
C
IN
Logic Inputs 1.5 5 pF
C
OUT
Output pin capacitance 6 pF
C
IN X
X1 & X2 pins 6 pF
SMBus Voltage
V
DD
2.7 5.5 V
Low-level Output Voltage V
OLSMB
@ I
PUL LUP
0.4 V
Current sinking at
V
OLSMB
= 0.4 V
I
PULLUP
SMB Data Pin 4 mA
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(
Min VIH + 0.15
)
1000 ns
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(M in VIH + 0.1 5) to
(
Max VIL - 0.15
)
300 ns
Maximum SMBus Operating Frequency F
SMBUS
100 kHz
Spread Spectrum Modula tion Frequency
f
SSM OD
Triangu lar Modulation 30 32.5 33 kH z
1
O
p
eration at these
p
oints is not recommended
4
O
p
eration under these conditions is nei ther im
p
lied
,
nor
g
uaranteed.
5
S ignal is required to be monotonic in this region.
6
Input leakage current does not include inputs with pull-up or pull-down resistors
Ambient Operating Temp
Operating Supply Current
Powerdown Cu rrent
Input Capacitance
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
2
Maximum VIH is not to exceed VDD
3
Human Bod
y
Model
8
For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm
7
3.3V referenced inputs are: PCI&PCIEX_STOP #, CPU_STOP#, ITP_EN, SCLK, SDATA, VTT_PWR_GD/PD#, SEL12_48# and PEREQ# inputs if selected.
IDT
®
Low Power Clock for Intel Atom
®
-Based Systems 1561C — 08/24/11
9LPRS436C
Low Power Clock for Intel Atom
®
-Based Systems
9
AC Electrical Characteristics - Input/Common Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
C lk Stabilization
T
STAB
From VDD Power-Up or de-assertion of PD to
1st clock
1.1 1 .8 ms
Td rive_PEREQ_off
T
DRPEROFF
Output stop after PEREQ# deasserted 2 3 clocks
Td rive_PEREQ_on T
DRPERON
Output run after PEREQ# a sserted 2 3 clocks
Tdrive_CPU
T
DRSR C
CPU output enable after
CPU_STOP# de-assertion
810ns
Tdrive_PCIEX
T
DRPCIEX
PCIEX output enab le after
PCI&PCIEX_STOP# de-assertion
815ns1
Tfall_SE
T
FALL
10 ns
Trise_SE T
RISE
10 ns
Td r iv e_P D#
T
DRPD
Differential output enable after
PD# de-assertion
85 300 us 1
Fall/rise time of all 3.3V control inputs from 20-
80%
AC Electrical Characteristics - CPU, PCIEX, SATA, DOT96MHz
P ARAME TE R SYMB O L C OND ITIONS M IN TY P MA X UNITS NOTE S
Rising Edge Slew Rate tSLR Different ial Measurement 2.5 3.3 4 V/ns 1,2
Falling Edge Slew Rate tFLR Differential Measurement 2.5 3.2 4 V/ns 1, 2
Slew Rate Variation tSLVAR Single-ended Measurement 16 20 % 1
Maximum Output Voltage VHIGH Includes overshoot 806 1150 mV 1
Minimum Output Voltage VLOW Includes undershoot -300 mV 1
Differential Voltage Swing VSWING Differential Measurement 30 0 mV 1
Crossin
g
Point Volta
g
eVXABSSin
g
le-ended Measurement 300 395 550 mV 1,3,4
Crossin
g
Point Variation VXABSVAR Sin
g
le-ended Measurement 32 140 mV 1,3,5
Dut
y
C
y
cle DCYC Differential Measurement 45 49.7 55 % 1
CPU Jitter - C
y
cle to C
y
cle CPUJC2C Differential Measurement 66 85
p
s1
CPU2_IPT Jitter - C
y
cle to C
y
cle CPU2JC2C Differential Measurement 125 150
p
s1
SRC Jitter - C
y
cle to C
y
cle SRCJC2C Differential Measurement 66 125
p
s1
SATA Jitter - C
y
cle to C
y
cle SATAJC2C Differential Measurement 66 125
p
s1
DOT Jitter - C
y
cle to C
y
cle DOTJC2C Differential Measurement 65 250
p
s1
CPU
[
1:0
]
Skew CPUSKEW10 Differential Measurement 38 100
p
s1,6
CPU
[
2_ITP:0
]
Skew CPUSKEW20 Differential Measurement 145 150
p
s1,6
SRC Skew SRCSKEW Differential Measurement 44 250
p
s1
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER SYMBOL CONDITIONS MIN
TY P
MAX UNITS
NOTES
Output Impedance R
DSP
V
O
= V
DD
*(0.5) 12 55
Ω
1
Long Accuracy ppm see Tperiod min-max values -100 100 ppm 2
33.33MHz output no spread 29.99700 30.00300 ns 2
33.33MHz output spread 30.08421 30.23459 ns 2
33.33MHz output no spread 29.49700 30.50300 ns 2
33.33MHz output nominal/spread 29.56617 30.58421 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V
1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
V
OH
@MIN = 1.0 V
-33 mA 1
V
OH
@MAX = 3.135 V
-33 mA 1
V
OL
@ MIN = 1. 95 V 30 mA 1
V
OL
@ MAX = 0.4 V
38 mA 1
Rising Edge Slew Rate t
SLR
Measured from 0.8 to 2.0 V 1 1.7 4 V/ns 1
Falling Edge Slew Rate
t
FLR
Measured from 2.0 to 0.8 V 1 1.8 4 V/ns 1
Duty Cycle
d
t1
V
T
= 1.5 V 45 50.6 55
%1
Pin to Pin Skew t
sk ew
V
T
= 1.5 V 250 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V 150 500 ps
1
*T
A
= Tambient ; V
DD
= 3.3 V +/-5%; C
L
=5pF, Rs=22
Ω
(unless specified otherwise)
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro d u ct io n.
2
All Lon
g
Term Ac c urac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFOUT is at 14.31818MHz
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#.
5
Only applies to the differential rising edge (Clock rising, Clock# falling.)
I
OH
Output High Current
T
abs
T
period
Output Low Current I
OL
Clock period
Absolute min/max period
6
CPU group skew is nominally 0ps.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

9LPRS436CKILF

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Manufacturer:
IDT
Description:
Clock Generators & Support Products ATOM NETTOP/NETBOOK
Lifecycle:
New from this manufacturer.
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