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UJA1076ATW/3V3/1J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 10 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.2 SPI
6.2.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCSN: SPI chip select; active LOW
• SCK: SPI clock; default level is LOW due to low-power concept
• SDI: SPI data input
• SDO: SPI data output; floating when pin SCSN is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge (see Figure 4
).
6.2.2 Register map
The first three bits (A2, A1 and A0) of the message header define the register address.
The fourth bit (RO) defines the selected register as read/write or read only.
Fig 4. SPI timing protocol
SCSN
SCK
01
sampled
floating floating
015aaa20
5
X
X
MSB 14 13 12 01 LSB
MSB 14 13 12 01 LSB
X
SDI
SDO
02 03 04 15 16
Table 3. Register map
Address bits 15, 14 and 13 Write access bit 12 = 0 Read/Write access bits 11... 0
000 0 = read/write, 1 = read only WD_and_Status register
001 0 = read/write, 1 = read only Mode_Control register
010 0 = read/write, 1 = read only Int_Control register
011 0 = read/write, 1 = read only Int_Status register
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 11 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.2.3 WD_and_Status register
[1] Bit NWP is set to its default value (100) after a reset.
Table 4. WD_and_Status register
Bit Symbol Access Power-on
default
Description
15:13 A2, A1, A0 R 000 register address
12 RO R/W 0 access status
0: register set to read/write
1: register set to read only
11 WMC R/W 0 watchdog mode control
0: Normal mode: watchdog in Window mode; Standby mode: watchdog in
Timeout mode
1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in
Off mode
10:8 NWP
[1]
R/W 100 nominal watchdog period
000: 8 ms
001: 16 ms
010: 32 ms
011: 64 ms
100: 128 ms
101: 256 ms
110: 1024 ms
111: 4096 ms
7 WOS/SWR R/W - watchdog off status/software reset
0: WDOFF pin LOW; watchdog mode determined by bit WMC
1: watchdog disabled due to HIGH level on pin WDOFF; results in software
reset
6 V1S R - V1 status
0: V1 output voltage above 90 % undervoltage recovery threshold
(V
uvr
;seeTable 10)
1: V1 output voltage below 90 % undervoltage detection threshold
(V
uvd
;seeTable 1 0)
5 V2S R - V2 status
0: V2 output voltage above undervoltage release threshold
(V
uvr
;seeTable 10)
1: V2 output voltage below undervoltage detection threshold
(V
uvd
;seeTable 1 0)
4 WLS1 R - wake-up 1 status
0: WAKE1 input voltage below switching threshold (V
th(sw)
)
1: WAKE1 input voltage above switching threshold (V
th(sw)
)
3 WLS2 R - wake-up 2 status
0: WAKE2 input voltage below switching threshold (V
th(sw)
)
1: WAKE2 input voltage above switching threshold (V
th(sw)
)
2:0 reserved R 000
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 12 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.2.4 Mode_Control register
[1] Bit LHWC is set to 1 after a reset.
[2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.
Table 5. Mode_Control register
Bit Symbol Access Power-on
default
Description
15:13 A2, A1, A0 R 001 register address
12 RO R/W 0 access status
0: register set to read/write
1: register set to read only
11:10 MC R/W 00 mode control
00: Standby mode
01: Sleep mode
10: Normal mode; V2 off
11: Normal mode; V2 on
9LHWC
[1]
R/W 1 limp home warning control
0: no limp home warning
1: limp home warning is set; next reset will activate LIMP output
8LHC
[2]
R/W 0 limp home control
0: LIMP pin set floating
1: LIMP pin driven LOW
7 ENC R/W 0 enable control
0: EN pin driven LOW
1: EN pin driven HIGH in Normal mode
6 reserved R 0
5 WBC R/W 0 wake bias control
0: pin WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1
1: pin WBIAS LOW if WSEn = 0; 64 ms sampling if WSEn = 1
4 PDC R/W 0 power distribution control
0: V1 threshold current for activating the external PNP transistor; load current
rising; I
th(act)PNP
= 85 mA; V1 threshold current for deactivating the external
PNP transistor; load current falling; I
th(deact)PNP
=50mA; see Figure 7
1: V1 threshold current for activating the external PNP transistor; load current
rising; I
th(act)PNP
= 50 mA; V1 threshold current for deactivating the external
PNP transistor; load current falling; I
th(deact)PNP
=15mA; see Figure 7
3:0 reserved R 0000
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

UJA1076ATW/3V3/1J

Mfr. #:
Buy UJA1076ATW/3V3/1J
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1076ATW/HTSSOP32//3V3/1/REEL 13 Q1 NDP
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New from this manufacturer.
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