UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 19 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load
current of 250 mA with PDC = 0. Any additional load current requirement will be supplied
by the PNP transistor, up to its current limit. If the load current continues to rise, I
V1
will
increase above the selected PDC threshold (to a maximum of 250 mA).
For a fast ramping load current, V1 will deliver the required load current (to a maximum of
250 mA) until the PNP transistor has switched on. Once the transistor has been activated,
V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load
current (see Figure 8
).
Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)
Fig 8. V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)
015aaa11
1
250 mA
85 mA
50 mA
load
current
215 mA
165 mA
PNP
current
I
V1
I
th(act)PNP
= 85 mA
(PDC = 0)
I
th(deact)PNP
= 50 mA
(PDC = 0)
load
current
250 mA
165 mA
0 mA
I
V1
165 mA
250 mA
PNP
current
015aaa075
I
th(act)PNP
= 85 mA
(PDC = 0)
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 20 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
For short-circuit protection, a resistor needs to be connected between pins V1 and
VEXCC to allow the current to be monitored. This resistor limits the current delivered by
the external transistor. If the voltage difference between pins VEXCC and V1 reaches
V
th(act)Ilim
, the PNP current limiting activation threshold voltage, the transistor current will
not increase further.
The thermal performance of the transistor needs to be considered when calculating the
value of this resistor. A 3.3 Ω resistor was used with the BCP52-16
(NXP Semiconductors) employed during testing. Note that the selection of the transistor is
not critical. In general, any PNP transistor with a current amplification factor (β) of
between 60 and 500 can be used.
If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin
VEXCTRL can be left open.
One advantage of this scalable voltage regulator concept is that there are no PCB layout
restrictions when using the external PNP. The distance between the UJA1076A and the
external PNP doesn’t affect the stability of the regulator loop because the loop is realized
within the UJA1076A. Therefore, it is recommended that the distance between the
UJA1076A and PNP transistor be maximized for optimal thermal distribution.
The output voltage on V1 is monitored continuously and a system reset signal is
generated if an undervoltage event occurs. A system reset is generated if the voltage on
V1 falls below the undervoltage detection voltage (V
uvd
; see Table 10). The reset
threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit
(RTHC) in the Int_Control register (Table 6
). In addition, an undervoltage warning (a V1UI
interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be
read via bit V1S in the WD_and_Status register (Table 4
).
6.6.3 Voltage regulator V2
Voltage regulator V2 is reserved for the high-speed CAN transceiver, providing a 5 V
supply.
V2 can be activated and deactivated via the MC bits in the Mode_Control register
(Table 5
). An undervoltage warning (a V2UI interrupt) is generated when the output
voltage drops below 90 % of its nominal value. The status of V2 can be read via bit V2S in
the WD_and_Status register (Table 4
) in Normal mode (V2S = 1 in all other modes).
V2 can be deactivated (MC = 10) to allow the internal CAN transceiver to be supplied from
an external source or from V1. The alternative voltage source must be connected to pin
V2. All internal functions (e.g. undervoltage protection) will work normally.
6.7 CAN transceiver
The analog section of the UJA1076A CAN transceiver corresponds to that integrated into
the TJA1042/TJA1043. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN
applications in the automotive industry, providing differential transmit and receive
capability to a CAN protocol controller.
6.7.1 CAN operating modes
6.7.1.1 Active mode
The CAN transceiver is in Active mode when:
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 21 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
the SBC is in Normal mode (MC = 10 or 11)
the transceiver is enabled (bit STBCC = 0; see Table 6)
and
V2 is enabled and its output voltage is above its undervoltage threshold, V
uvd
or
V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its
undervoltage threshold (see Section 6.6.3
)
In CAN Active mode, the transceiver can transmit and receive data via the CANH and
CANL pins. The differential receiver converts the analog data on the bus lines into digital
data which is output on pin RXDC. The transmitter converts digital data generated by a
CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus
lines.
6.7.1.2 Lowpower/Off modes
The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCC = 1 (see Table 6
). The CAN transceiver can be woken up remotely via pins CANH
and CANL in Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver
will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or ElectroMagnetic Interferance (EMI).
A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within
the wake-up timeout time (t
to(wake)
) to pass the wake-up filter and trigger a wake-up event
(see Figure 9
; note that additional pulses may occur between the recessive/dominant
phases). The minimum recessive/dominant bus times for CAN transceiver wake-up
(t
wake(busrec)min
and t
wake(busdom)min
) must be satisfied (see Table 11).
Fig 9. CAN wake-up timing diagram
recessivedominantrecessive dominant
wake-up
015aaa10
7
t
wake
< t
to(wake)

UJA1076ATW/3V3/1J

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1076ATW/HTSSOP32//3V3/1/REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
Delivery:
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