UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 17 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.5.1 RSTN pin
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t
fltr
by
the microcontroller (external reset). A reset pulse is output on pin RSTN by the SBC when
a system reset is triggered internally.
The reset pulse width (t
w(rst)
) is selectable (short or long) if the system reset was
generated by a V1 undervoltage event (see Section 6.6.2
) or by the SBC leaving Off
(V
BAT
> V
th(det)pon
) or Overtemp (temperature < T
th(rel)otp
) modes. A short reset pulse is
selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1. If a resistor is
not connected, the reset pulse will be long (see Table 11
).
In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.
6.5.2 EN output
The EN pin can be used to control external hardware, such as power components, or as a
general-purpose output when the system is running properly.
In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in
the Mode_Control register; see Table 5
) via the SPI interface. Pin EN will be HIGH when
ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior
is illustrated in Figure 5
.
6.5.3 LIMP output
The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an
ECU failure. Detectable failure conditions include SBC overtemperature events, loss of
watchdog service, pins RSTN or V1 clamped LOW and user-initiated or external reset
events.
The LIMP pin is a battery-related, active-LOW, open-drain output.
A system reset will cause the limp home warning control bit (bit LHWC in the
Mode_Control register; see Table 5
) to be set. If LHWC is already set when the system
reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application
should clear LHWC after each reset event to ensure the LIMP output is not activated
during normal operation.
In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always
active. If the application manages to recover from the event that activated the LIMP
output, LHC can be cleared to deactivate the LIMP output.
Fig 5. Behavior of EN pin
RSTN
EN
ENC
mode
STANDBY NORMAL STANDBY
015aaa07
