UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 22 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.7.2 Split circuit
Pin SPLIT provides a DC stabilized voltage of 0.5V
V2
. It is activated in CAN Active mode
only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V
SPLIT
circuit can be
used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the
center tap of the split termination (see Figure 10
).
A transceiver in the network that is not supplied and that generates a significant leakage
current from the bus lines to ground, can result in a recessive bus voltage of < 0.5V
V2
. In
this event, the split circuit will stabilize the recessive voltage at 0.5V
V2
. So a start of
transmission will not generate a step in the common-mode signal which would lead to
poor ElectroMagnetic Emission (EME) performance.
6.7.3 Fail-safe features
6.7.3.1 TXDC dominant time-out function
A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW
state on pin TXDC persists for longer than the TXDC dominant time-out time (t
to(dom)TXDC
),
the transmitter will be disabled, releasing the bus lines to recessive state. This function
prevents a hardware and/or software application failure from driving the bus lines to a
permanent dominant state (blocking all network communications). The TXDC dominant
time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time
also defines the minimum possible bit rate of 10 kbit/s.
6.7.3.2 Pull-up on TXDC pin
Pin TXDC has an internal pull-up towards V
V1
to ensure a safe defined state in case the
pin is left floating.
6.8 Local wake-up input
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register Table 6
). These bits can also be used to disable
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
Fig 10. Stabilization circuitry and application using the SPLIT pin
UJA1076A
V2
CANL
SPLIT
CANH
60 Ω
60 Ω
R
R
GND
V
SPLIT
= 0.5 V
CC
in normal mode;
otherwise floating
015aaa19
