UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 9 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
6.1.4 Normal mode
Normal mode is selected from Standby mode by setting bits MC in the Mode_Control
register (Table 5
) to 10 (V2 disabled) or 11 (V2 enabled).
In Normal mode, the CAN physical layer will be enabled (Active mode; STBCC = 0; see
Table 6
) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up
detection active.
The SBC will exit Normal mode if:
• Standby mode is selected by setting bits MC to 00
• Sleep mode is selected by setting bits MC to 01
• A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode)
• The chip temperature rises above the OTP activation threshold, T
th(act)otp
, causing the
SBC to switch to Overtemp mode
6.1.5 Sleep mode
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the
Mode_Control register (Table 5
) to 01. The SBC will enter Sleep mode providing there are
no pending interrupts (pin INTN = HIGH) or wake-up events and at least one wake-up
source is enabled (CAN or WAKE). Any attempt to enter Sleep mode while one of these
conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width;
see Section 6.5.1
and Table 11).
In Sleep mode, V1 and V2 are off and the CAN transceiver will be switched off (Off mode;
STBCC = 0; see Table 6
) or in a low-power state (Lowpower mode; STBCC = 1) with bus
wake-up detection active - see Section 6.7.1
). The watchdog is off and the reset pin is
LOW.
A CAN or local wake-up event will cause the SBC to switch from Sleep mode to Standby
mode, generating a (short or long; see Section 6.5.1
) system reset. The value of the mode
control bits (MC) will be changed to 00 and V1 will be enabled.
6.1.6 Overtemp mode
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip
temperature exceeds the overtemperature protection activation threshold, T
th(act)otp
,
In Overtemp mode, the voltage regulators are switched off and the bus system is in a
high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW
and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.
The chip temperature must drop a hysteresis level below the overtemperature shutdown
threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the
SBC enters Standby mode and a system reset is generated (reset pulse width of t
w(rst)
,
long or short; see Section 6.5.1
and Table 11).
