D2-41051, D2-41151
12
FN6783.1
May 5, 2016
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Overview
The D2-41x51-QR devices are integrated System-on-Chip (SoC)
audio processor and Class D amplifier PWM controller. They
include complete digital audio input selection, signal routing,
complete audio processing, and selectable PWM output options
for driving multiple output power stage configurations. Stereo I
2
S
and stereo S/PDIF digital input support, plus I
2
C and 2-wire SPI
control interfaces enable integration compatibility with existing
system architectures and solutions. The audio path includes a
stereo Sample Rate Converter (SRC) plus device-specific audio
enhancement processing algorithms.
Output Configurations
A 5-channel PWM engine with application-selected configuration
settings provides output paths for combinations of output
channels. Application dependent configuration selection includes
PWM controller outputs for driving Stereo Speaker, 2.1 Speaker,
and Stereo Bi-Amp Speaker solutions, as well as Stereo Line,
Headphone Outputs, or Subwoofer Line Outputs. Depending on
configuration settings, Full-Bridge, Half-Bridge and Bridge-Tied-
Load (BTL) output stage topologies, with either discrete or
integrated output stages are supported.
Programmable Audio Processing
Programmable parameter settings for audio processing include
volume control, path routing and mixing, high/low pass filtering,
multi-band equalizers, compressors, and loudness. These
parameters can be adjusted using the D2Audio™ Canvas II™
software during design and development, or can be set through
the device’s control interface within production amplifier
products.
Typical Performance
Final system performance is largely determined by the amplifier
configuration, its choice of output power stages and
components, and overall system design. Typical performance
capability of amplifier power outputs varies from less than 10
Watts to systems over 150 Watts. System audio performance
includes 20Hz to 20kHz frequency response, SNR of greater than
100dB, and THD+N performance typically below 0.1%.
Audio Enhancement Processing
The D2-41x51-QR devices include D2Audio™ SoundSuite™
(within the D2-41051 device) and DTS®(SRS) WOW/HD™ (within
the D2-41151 device) audio enhancement algorithms. These
functions are integrated within the firmware of each device, and
are part of the standard audio signal flow.
Functional Description
Figure 4 shows a block diagram of the D2-41x51-QR devices, and
serves as a reference for many of the items in the following
descriptions. Additional information, including detailed
programming and parameter data, communication detail, and
amplifier design implementation is described in the
D2-41x51-QR Technical Reference document, available from
Intersil Corporation.
43 CVDD P 3.3 - Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.
44 nRSTOUT O 3.3 16 - OD Active low output. Pin drives low from 3.3V brownout detector or 1.8V brownout
detector going active. This output should be used to initiate a system reset to the
nRESET pin upon brownout event detection.
45 nRESET I 3.3 - Active low reset input with hysteresis. Low level activates system level reset,
initializing all internal logic and program operations. System latches boot mode
selection on the IRQ input pins on the rising edge.
46 TEMPCOM/
TIO0
I/O 3.3 16 Temperature monitor common I/O pin.
47 SDA I/O 3.3 8 - OD Two-Wire Serial data port, open drain driver with 8mA drive strength. Bidirectional
signal used by both the master and slave controllers for data transport. Pin floats
on reset.
48 SCL I/O 3.3 8 - OD Two-Wire Serial clock port, open drain driver with 8mA drive strength. Bidirectional
signal is used by both the master and slave controllers for clock signaling. Pin
floats on reset.
NOTES:
14. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix, such as nRESET.
15. OD means pad has open drain driver.
16. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., RVDD pins to be tied together, RGND pins
tied together, CVDD pins tied together, CGND pins to be tied together, PWMVDD pins tied together, PWMGND pins tied together, etc.)
D2-41051, D2-41151 Pin Descriptions (Continued)
PIN
PIN NAME
(Notes 14
, 16)TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
(Note 15
)DESCRIPTION
