D2-41051, D2-41151
17
FN6783.1
May 5, 2016
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Temperature Sensing
The temperature sensing algorithm utilizes external hardware on
the amplifier’s design to monitor system temperature. This
external hardware includes a negative temperature coefficient
(NTC) resistor located physically on the design in an areas that
require monitoring.
This operation uses three of the I/O pins (TEMPREF/SCK,
TEMP1/MOSI, and TEMPCOM/TIO1). These pins have shared
functions. During device initialization, these pins operate as part
of the SPI interface, but after the firmware is executing, the SPI
functionality turns off and these pins are dedicated to the
temperature monitoring function.
Overcurrent Sensing
Overcurrent sensing is accomplished with current threshold
detectors connected in the power supply used at each power
stage output of the amplifier design.
Design of these detectors is described in the D2-41x51-QR
Technical Reference document, but their purpose is to generate a
pulse or logic level upon detection of high current, where this
logic level is connected to one of the three protection input
(PROTECT[0:2]) pins.
These protection input pins are primarily intended for protecting the
PWM powered output stages. They are activated by either a pulse or
level driven into the pin. Firmware within the D2-41x51-QR devices
monitors the internal hardware connected to these pins, and adjusts
or disables the PWM output drive, depending on the conditions
monitored on these protection input pins.
The number of powered outputs in a design depends on which
one of the four configurations is defined. The configuration
settings, established upon device reset through the configuration
pins, also determines which of the protection inputs are used.
Power Supply Synchronization
The PSSYNC/CFG1 pin provides a power supply synchronization
signal for switching power supplies. Firmware configures this pin
to the frequency and duty cycle needed by the system switching
regulator. This synchronization allows switching supplies used
with the device to operate without generating in-band audio
interference signals that could be possible if the switching power
supply is not locked to the amplifier switching.
This PSSYNC/CFG1 pin is a shared pin. During device reset and
initialization, it operates as one of two configuration input pins,
where its high or low logic state is used to set the amplifier
configuration mode. After completion of reset and when the
device firmware begins operating, this pin becomes the PSSYNC
output.
Error Reporting
Internal monitoring of system and device operation uses an I/O
pin (nERROR/CFG1) as an output to signal an external system
controller of a channel shutdown error condition. This output may
be used to turn on a simple indicator.
The error output is also used to signal an external microcontroller
that the I
2
C bus may be busy. When the error output is low during
system initialization, the I
2
C bus is busy as a master device.
This error output is active low and only becomes used as an
output after the device firmware has initialized and began
running. This same pin is shared as an input. During a reset
condition, this pin operates as an input, and is one of two input
pins that are used to define the configuration mode. A resistor
pull-up or pull-down on this pin establishes this mode input
configuration state. After completion of the initialization
sequence, these resistors do not affect the error output
operation.
Power Sequencing
The CVDD and RVDD (including PWMVDD) power supplies should
be brought up together to avoid high current transients that could
fold back a power supply regulator. The PLLVDD may be brought
up separately. Best practice would be for all supplies to feed from
regulators with a common power source. Typically this can be
achieved by using a single 5V power source and regulating the
3.3V and 1.8V supplies from that 5V source. As noted in the pin
specifications of this document, all voltages of the same names
must be tied together at the board level.
Clock and PLL
Clock is generated on-chip, using a fundamental-mode crystal
connected across the XTALI and XTALO pins. XTALO is an output,
but is designed only to drive the crystal, and not connect to any
other circuit. XTALI is an input, connecting to the other side of the
crystal.
The clock generation contains a low jitter PLL critical for low
noise PWM output and a precise master clock source for sample
rate conversion and the audio processing data paths. The clock
system is used throughout the device, and provides clock
generators for brown-out detection, system and power-on reset,
DSP, S/PDIF transmitter, and the PWM engine.
Clock and PLL hardware functions are controlled by internal
device firmware. They are not programmable and are optimized
for device and system operation.
Reset and Device Initialization
The D2-41x51-QR devices must be reset to initialize and begin
proper operation. A system reset is initiated by applying a low level
to the nRESET input pin. External hardware circuitry or a controller
within the amplifier system design must provide this reset signal
and connect to the nRESET input to initiate the reset process.
Device initialization then begins after the nRESET pin is released
from its low-active state.
The chip contains power rail sensors and brownout detectors on
the 3.3V and 1.8V power supplies. A loss or droop of power from
either of these supplies will trigger their brownout detectors which
will assert the nRSTOUT pin, driving it low. This pin should connect
to the nRESET input through hardware on the amplifier design, to
ensure a proper reset occurs if the power supply voltages drop
below their design specifications. Refer to the D2-41x51-QR
Technical Reference document for connection recommendations.
At the deassertion of nRESET, the chip will read the status of the
boot mode selection pins (IRQA and IRQB) and begin the boot
process, determined by the boot mode that is defined by these
pins’ logic state. These device pins are strapped either high or
low on the system’s design (PCB), and it is the state of these pins
