D2-41051, D2-41151
7
FN6783.1
May 5, 2016
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Two-Wire (I
2
C) Interface Port Timing T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at
0.0V. All voltages referenced to ground.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
fSCL SCL Frequency --100kHz
t
buf
Bus Free Time Between Transmissions 4.7 - - µs
t
wlow
SCLx SCL Clock Low 4.7 - - µs
t
whigh
SCLx SCL Clock High 4.0 - - µs
t
s
STA Set-Up Time for a (Repeated) Start 4.7 - - µs
t
h
STA Start Condition Hold Time 4.0 - - µs
t
h
SDAx SDA Hold from SCL Falling (See Note 12) - 1 - sys clk
t
s
SDAx SDA Set-Up Time to SCL Rising 250 - - ns
t
d
SDAx SDA Output Delay Time from SCL Falling - - 3.5 µs
t
r
Rise Time of Both SDA and SCL (See Note 13) - - 1 µs
t
f
Fall Time of Both SDA and SCL (See Note 13) - - 300 ns
t
s
STO Set-Up Time for a Stop Condition 4.7 - - µs
NOTES:
12. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
13. Limits established by characterization and not production tested.
t
wlow
SCLx
SCLx
SDAx
(INPUT)
t
s
STA
t
h
STAx
t
r
t
f
t
s
SDAx
t
h
SDAx t
s
STO
t
buf
SDAx
(OUTPUT)
t
d
SDAx
t
whigh
SCLx
FIGURE 2. I
2
C INTERFACE TIMING
