D2-41051, D2-41151
4
FN6783.1
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Specifications
Absolute Maximum Ratings (Note 7) Thermal Information
Supply Voltage
RVDD, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD + 0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD + 0.3V
Input Current, any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
48 Ld QFN (Notes 5
, 6) . . . . . . . . . . . . . . . . 27 2
Temperature Range (Operating) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
.
6. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
7. Absolute Maximum parameters are not tested in production.
Recommended Operating Conditions T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds
at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic.
SYMBOL PARAMETER MIN TYP MAX UNIT
CVDD Core Supply Pins 1.7 1.8 1.9 V
Active Current - 300 - mA
Power-Down Current (Note 8
)-6-mA
RVDD and PWMVDD Digital I/O and PWM Pad Ring Supply Pins 3.0 3.3 3.6 V
Active Current - 10 - mA
Power-Down Current (Note 8
) - 0.01 - mA
PLLVDD Analog Supply Pins (PLL) 1.7 1.8 1.9 V
Active Current - 10 - mA
Power-Down Current (Note 8
)-5-mA
NOTE:
8. Power Down is with device in reset and clocks stopped
Electrical Specifications T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic.
SYMBOL PARAMETER MIN TYP MAX UNIT
V
IH
Digital Input High Logic Level (Note 9)2--V
V
IL
Digital Input Low Logic Level (Note 9)--0.8V
V
OH
High Level Output Drive Voltage (Note 10) (I
OUT
= -Pad Drive) RVDD - 0.4 - - V
V
OL
Low Level Output Drive Voltage (Note 10) (I
OUT
= +Pad Drive) - - 0.4 V
V
IHX
High Level Input Drive Voltage XTALI Pin 0.7 - PLLVDD V
V
ILX
Low Level Input Drive Voltage XTALI Pin - - 0.3 V
I
IN
Input Leakage Current (Note 11)--±10µA
C
IN
Input Capacitance -9-pF
C
OUT
Output Capacitance -9-pF
Trst nRESET Pulse Width -10-ns
D2-41051, D2-41151
5
FN6783.1
May 5, 2016
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CRYSTAL OSCILLATOR
Xo Crystal Frequency (Fundamental Mode Crystal) 20 24.576 25 MHz
Dt Duty Cycle 40 - 60 %
Tstart Start-Up Time (Start-Up Time is Oscillator enabled (with Valid Supply) to Stable Oscillation) - 5 20 ms
PLL
Fvco VCO Frequency 240 294.912 300 MHz
PLL Lock Time from any Input Change - 3 - ms
1.8V POWER ON RESET
Ven Reset Enabled Voltage Level 0.95 1.10 1.30 V
Tdis POR Minimum Output Pulse Width - 5 - µs
1.8V BROWNOUT DETECTION
Detect Level 1.4 1.5 1.7 V
Tbod1 Pulse Width Rejection - 100 - ns
To1 Minimum Output Pulse Width - 20 - ns
3.3V (CVDD) BROWNOUT DETECTION
Detect Level 2.4 2.7 2.9 V
Tbod3 Pulse Width Rejection - 100 - ns
To3 Minimum Output Pulse Width - 20 - ns
NOTES:
9. All input pins except XTALI
10. All digital output pins. Drive strength for each digital pin is in the
D2-41051, D2-41151 Pin Descriptions” on page 10.
11. Input leakage applies to all pins except XTALO
Electrical Specifications T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. (Continued)
SYMBOL PARAMETER MIN TYP MAX UNIT
D2-41051, D2-41151
6
FN6783.1
May 5, 2016
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Serial Audio Interface Port Timing T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%, XTALI = 24.576
MHz, NESSI clock polarity = 1. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
c
SCLK SCLK Frequency - (SCLK) - - 12.5 MHz
t
w
SCLK SCLK Pulse Width (HIGH and LOW) - (Sclk) 40 - - ns
t
s
LRCLK LRCKR Set-Up to SCLK Rising - (LRCK) 20 - - ns
t
h
LRCLK LRCKR Hold from SCLK Rising - (LRCK) 20 - - ns
t
s
SDI SDIN Set-Up to SCLK Rising - (SDIN) 20 - - ns
t
h
SDI SDIN Hold from SCLK Rising - (SDIN) 20 - - ns
t
c
SCLK
LRCK
SCLK
SDIN
t
h
LRCLK
t
s
LRCLK t
s
SDI
t
h
SDI
t
w
SCLK
t
w
SCLK
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING

D2-41051-QR-TK

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Audio DSPs DAE-4 AUD PROCESSOR: SS & CUSTOM CODE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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