D2-41051, D2-41151
15
FN6783.1
May 5, 2016
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Audio Enhancement Feature Processing
Additional enhancement audio processing algorithms are
included within specific part number options of the
D2-41x51-QR devices. These specific enhancements are:
• D2Audio™ SoundSuite™ (WideSound™, DeepBass™, Audio
Align™, and ClearVoice™) Audio Processing
(with the D2-41051 device)
• DTS®SRS WOW/HD™
(with the D2-41151 device)
Each of these enhancements are unique only to the particular
part number, and each enhancement has its own set of
programmable parameters to control operation. The location of
these enhancements within the signal flow is shown in Figure 5
on page 16.
PWM Audio Outputs
The D2-41x51-QR devices incorporate five PWM output channels
that are mapped to eight PWM output pins. Each of the PWM
channels and their pins are used for driving output power stages,
and/or for line level outputs, depending on the selected
configuration mode.
The outputs support multiple PWM amplifier output topologies.
These supported topologies include half-bridge N+N or N+P, and
full-bridge N+N or N+P using 2-level modulation with 2 or
4-quadrant control. The channel and function assignment of the
eight output pins as well as the associated output topology is
established by the output mode configuration settings. Refer to
“
Output Mode Configurations” on page 18 for description and
selection of these output configurations, and their associated
mapping of the PWM output pins. Also refer to the D2-41x51-QR
Technical Reference document for additional operation of the
outputs.
Using a simple passive filter, the PWM outputs will drive line-level
outputs at a nominal 1V
rms
. Headphone outputs or line-level
outputs that require a 2V
rms
or higher output level are
implemented using an active filter.
I/O Control Pins
Several device pins are used as specific-function inputs and
outputs and are used to control amplifier and device operation.
Some pins are multiple-purpose, where their functions are
different depending on the device operating state. Functions of
these pins are defined in the pin definition list, and additional
descriptions are included within the functional block descriptions
elsewhere in this document. These pins are implemented within
the device hardware as general purpose inputs/outputs.
However, their operation is not programmable, and their specific
function is defined by the D2-41x51-QR internal firmware.
Timers
There are two independent timers used for device and system
control. One timer is used for internal references, and the other is
used for the temperature sensing control. There are two I/O pins
associated with the timers, and these pin functions are defined
by the device firmware. Timer 0 is used for the timing-related
executions of the temperature monitoring algorithm. Its pin
(TIO0) is used as an input and output for that temperature
monitoring operation. Timer 1 is used for internal functions of the
device. Its pin (TIO1) is not used for this timing operation, and is
defined by device firmware as the nMUTE I/O pin. Timer
operation is established internally by firmware and not
programmable.
I
2
C 2-Wire Control Interface
The D2-41x51-QR devices include a 2-Wire I
2
C compatible
interface for communicating with an external controller.
This interface is usable with either an external microcontroller
interface, or for communication to EEPROMs, or other
compatible peripheral chips. The I
2
C interface is multi-master
capable, operates as independent master and slave, and
supports normal and fast mode operation.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an alternate serial input
port that provides an interface for loading parameter data from
an optional EEPROM or Flash device during boot-up operation.
The four SPI interface pins are all shared. This interface functions
only as an input port for external boot operation and does not
operate as an interactive control port. During a reset condition,
initiating the boot-up process, the four pins (TEMPREF/SCK,
TEMP1/MOSI, VOL1/MISO, VOL0/nSS) operate as the SPI port.
As soon as the boot-up process is completed and the device
begins executing its firmware program, these pins are no longer
used for SPI functions, and operate as assigned by the firmware.
Control Register Summary
The control register interface is used for an external controller to
adjust the amplifier’s programmable settings and adjustments
within its signal flow. These parameters for each of the signal
processing blocks are accessed through a register programming
interface, and each parameters is defined with its specific
register address. Audio input selection (I
2
S input or S/PDIF
receiver input) and output elements (PWM amplifier and line
outputs, and S/PDIF transmitter) are controlled through their
register parameters.
All of these control register functions are defined in the
Application Programming Interface (API) specification within the
D2-41x51-QR Technical Reference document.
