1998 May 15 29
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
Timing is compatible with SAA7110; I
2
C-bus bit FECO = 0.
handbook, full pagewidth
LLC
CREF
HREF
VPO
t
SU;DAT
t
HD;DAT
to 3-state
MGC657
from 3-state
t
OHD;DAT
t
PD
t
PDZ
FEI
Fig.20 Real time control output.
(1) Set to zero for one transmission, if a phase reset of the f
sc
− DTO is applied via I
2
C-bus bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (f
LFCO
× 4=f
LLC
); 16 LSB from 20, upper four bits are fixed to 0100b.
Where: f
XTAL
= 24.576 MHz, word length DTO2 = 20 bits.
The f
sc
increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
Where: word length DTO1 = 24 bits.
f
LFCO
INCR
HPLL
f
XTAL
×
2
word length DTO2
-------------------------------------------------
=
f
sc
INCR
FSCPLL
f
XTAL
×
2
word length DTO1
-------------------------------------------------------
INCR
HPLL
2
19
----------------------------
×=
handbook, full pagewidth
TIME SLOT:
BIT NO.:
transmitted once per line
22
1
21
1920
15
1617
18
7
8
9
11 1012
13
14
SEQUENCE
19
0 67
2
3
6
4
5
2
3
0
16
45
RESERVED
16
INCR
FSCPLL
MGC649
63
0
1
RESERVED
128
HIGH
LOW
15
INCR
HPLL
RESERVED
1
68
DTO RESET
(1)
50 Hz fields: 235
60 Hz fields: 232
