1998 May 15 37
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Notes to Table 5
1. VPO bus allows connection to 5 V video data bus systems.
2. Values in accordance with CCIR 601.
3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.
a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I
2
C-bus bit TCLO = 0
b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I
2
C-bus bit TCLO = 1.
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit
signals (after dithering if desired).
5. CREF = 0 (see Fig.17).
6. CREF = 1 (see Fig.17).
Fig.28 VPO output signal range with default BCS settings.
Equations for modification to the YUV levels via BCS control I
2
C-bus bytes BRIG, CONT and SATN.
Luminance:
Chrominance:
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Y
OUT
Int
CONT
71
------------------
Y128–()× BRIG+=
UV
OUT
Int
SATN
64
-----------------
Cr Cb, 128–()× 128+=
CCIR Rec. 602 digital levels.
a. Y output range. b. U output range (Cb). c. V output range (Cr).
handbook, full pagewidth
LUMINANCE 100%
+255
+235
+128
+16
0
white
black
U-COMPONENT
+255
+240
+212 +212
+128
+16
+44
0
blue 100%
blue 75%
yellow 75%
yellow 100%
colourless
V-COMPONENT
+255
+240
+128
+16
+44
0
red 100%
red 75%
cyan 75%
cyan 100%
colourless
MGC634
