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SAA7111AHZ/V4,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
1998 May 15 40
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Fig.32 Application diagram for RGB 24-bit output format.
I
2
C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6).
RGB888 = 1 (subaddress 12H, bit D3).
handbook, full pagewidth
OEN
D7
7
6
5
4
3
2
1
0
D6
D5
D4
e.g.
74HCT574
D3
D2
D1
D0
44
45
46
47
48
49
50
51
31
HREF
17
27
30
60
28
29
53
14
20
21
32
23
V
SS
V
SS
V
SS
CLK
O7
3
R (2 : 0)
R (7 : 0)
O6
O5
O4
O3
O2
O1
00
V
DD
V
DD
3
3
3
2
G (1 : 0)
G (7 : 0)
3
B (2 : 0)
B (7 : 0)
LLC2N
MGG073
LLC2
e.g. 74HCT240
B (7 : 3)VPO (4 : 0)
VPO
(7 : 0)
SAA7111A
VPO (15 : 11) R (7 : 3)
G (7 : 5)
G (4 : 2)
VPO (10 : 8)
VPO (7 : 5)
5
8
8
VREF
HS
VS
RTCO
RTS1
RTS0
GPSW
AOUT
LLC
CREF
RES
8
15
14
13
12
11
10
9
8
34
35
36
37
38
39
42
43
VPO
(15 : 8)
16.1 Layout hints
Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero Ω resistor. Use separate supply
lines for analog and digital supply. Place the supply
decoupling capacitors close to the supply pins.
Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.
1998 May 15 41
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
17 I
2
C-BUS DESCRIPTION
17.1 I
2
C-bus format
Table 7 Write procedure
Table 8 Read procedure (combined format)
Table 9 Description of I
2
C-bus format
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I
2
C-bus specification).
3. The I
2
C-bus subaddress 00 has to be initialized with 0 before being read.
S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s DATA (N BYTES) ACK-s P
S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s
Sr SLAVE ADDRESS R ACK-s DATA (N BYTES) ACK-m P
CODE DESCRIPTION
S START condition
Sr repeated START condition
Slave address W 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK-s acknowledge generated by the slave
ACK-m acknowledge generated by the master
Subaddress subaddress byte; see Table 10
Data data byte; see Table 10; note 1
P STOP condition
X = LSB slave
address
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
Slave address read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
Subaddresses 00H chip version read and write; note 3
01H reserved −
02h to 05H front-end part read and write
06H to 13H decoder part read and write
14H reserved −
15H to 17H decoder part read and write
18H to 19H reserved −
1AH to 1CH Line-21 text slicer part read only
1DH to 1EH reserved −
1FH status byte read only
1998 May 15 42
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Table 10 I
2
C-bus receiver/transmitter overview
Note
1. All unused control bits must be programmed with logic 0.
SLAVE ADDRESS
READ WRITE IICSA
49H
4BH
48H
4AH
0
1
REGISTER
FUNCTION
SUB-
ADDR
D7 D6 D5 D4 D3 D2 D1 D0
Chip version 00 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00
Reserved 01
(1) (1) (1) (1) (1) (1) (1) (1)
Analog input contr 1 02 FUSE1 FUSE0 GUDL2 GUDL1 GUDL0 MODE2 MODE1 MODE0
Analog input contr 2 03
(1)
HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18
Analog input contr 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10
Analog input contr 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20
Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
Sync control 08 AUFD FSEL EXFIL
(1)
VTRC HPLL VNOI1 VNOI0
Luminance control 09 BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0
Luminance
brightness
0A BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
Luminance contrast 0B CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
Chroma saturation 0C SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0
Chroma Hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0
Chroma control 0E CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0
Reserved 0F
(1) (1) (1) (1) (1) (1) (1) (1)
Format/delay control 10 OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0
Output control 1 11 GPSW CM99 FECO COMPO OEYC OEHV VIPB COLO
Output control 2 12 RTSE1 RTSE0 TCLO CBR RGB888 DIT AOSL1 AOSL0
Output control 3 13 VCTR1 VCTR0 CCTR1 CCTR0 BCHI1 BCHI0 BCLO1 BCLO0
Reserved 14
(1) (1) (1) (1) (1) (1) (1) (1)
V_GATE1_START 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0
V_GATE1_STOP 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0
V_GATE1_MSB 17
(1) (1) (1) (1) (1) (1)
VSTO8 VSTA8
Reserved 18-19
(1) (1) (1) (1) (1) (1) (1) (1)
Text slicer status 1A
(1) (1) (1) (1)
F2VAL F2RDY F1VAL F1RDY
Decoded bytes of
the text slicer
1B P1 BYTE16 BYTE15 BYTE14 BYTE13 BYTE12 BYTE11 BYTE10
1C P2 BYTE26 BYTE25 BYTE24 BYTE23 BYTE22 BYTE21 BYTE20
Reserved 1D-1E
(1) (1) (1) (1) (1) (1) (1) (1)
Status byte 1F STTC HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

SAA7111AHZ/V4,557

Mfr. #:
Buy SAA7111AHZ/V4,557
Manufacturer:
NXP Semiconductors
Description:
IC VIDEO INPUT PROCESSOR 64-LQFP
Lifecycle:
New from this manufacturer.
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