1998 May 15 34
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Table 3 Digital output control
Note
1. Only active in 656-format (OFTS = 3).
OEYC FEI TCLO
(1)
VPO
15 to 8
VPO
7to0
000 Z
1 0 0 active
010 Z
110 Z
001ZZ
1 0 1 active Z
011ZZ
111ZZ
14 CLOCK SYSTEM
14.1 Clock generation circuit
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internally
generated LFCO (triangular waveform) is multiplied by 4
via the analog PLL (including phase detector, loop filter,
VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
Table 4 Clock frequencies
CLOCK FREQUENCY (MHz)
XTAL 24.576
LLC 27
LLC2 13.5
LLC4 6.75
LLC8 3.375
Fig.26 Block diagram of clock generation circuit.
handbook, full pagewidth
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
DIVIDER
1/2
DIVIDER
1/2
OSCILLATOR
DELAY CREF
MGC632
LLC2
LLC
LFCO
1998 May 15 35
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
14.2 Power-on control
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below
2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
Fig.27 Power-on control circuit.
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked clock output;
RES = reset output (active LOW).
handbook, full pagewidth
MGC633
128 LCC
896 LCC
digital delay
some ms
20 to 200 µs
PLL-delay
<
1 ms
RES
LLC
RESINT
LLCINT
XTAL
CE
POC V
DDA
POC
LOGIC
ANALOG
POC V
DDD
DIGITAL
POC
DELAY
CLOCK
PLL
CE
LLC
CLK0
RES
1998 May 15 36
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Table 5 Power-on control sequence
15 OUTPUT FORMATS
Table 6 Output formats of the VPO bus (note 1)
INTERNAL POWER-ON CONTROL
SEQUENCE
PIN OUTPUT STATUS FUNCTION
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC,
LLC2 and CREF are in high-impedance
state
direct switching to high impedance for
20 to 200 ms
Synchronous reset sequence LLC, LLC2, CREF, RTCO, RTS0,
RTS1, GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state
internal reset sequence
Status after power-on control
sequence
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state
after power-on (reset sequence) a
complete I
2
C-bus transmission is
required
BUS
SIGNAL
411 (12-BIT)
422
(16-BIT)
(2)
CCIR-656 (8-BIT)
(3)
RGB (16-BIT)
(4)
RGB (24-BIT)
(4)
VPO15 Y
07
Y
17
Y
27
Y
37
Y
07
Y
17
U
07
Y
07
V
07
Y
17
R4 R7 R7
VPO14 Y
06
Y
16
Y
26
Y
36
Y
06
Y
16
U
06
Y
06
V
06
Y
16
R3 R6 R6
VPO13 Y
05
Y
15
Y
25
Y
35
Y
05
Y
15
U
05
Y
05
V
05
Y
15
R2 R5 R5
VPO12 Y
04
Y
14
Y
24
Y
34
Y
04
Y
14
U
04
Y
04
V
04
Y
14
R1 R4 R4
VPO11 Y
03
Y
13
Y
23
Y
33
Y
03
Y
13
U
03
Y
03
V
03
Y
13
R0 R3 R3
VPO10 Y
02
Y
12
Y
22
Y
32
Y
02
Y
12
U
02
Y
02
V
02
Y
12
G5 G7 G7
VPO9 Y
01
Y
11
Y
21
Y
31
Y
01
Y
11
U
01
Y
01
V
01
Y
11
G4 G6 G6
VPO8 Y
00
Y
10
Y
20
Y
30
Y
00
Y
10
U
00
Y
00
V
00
Y
10
G3 G5 G5
VPO7 U
07
U
05
U
03
U
01
U
07
V
07
X X X X G2 G4 R2
VPO6 U
06
U
04
U
02
U
00
U
06
V
06
X X X X G1 G3 R1
VPO5 V
07
V
05
V
03
V
01
U
05
V
05
X X X X G0 G2 R0
VPO4 V
06
V
04
V
02
V
00
U
04
V
04
X X X X B4 B7 G1
VPO3 X X X X U
03
V
03
X X X X B3 B6 G0
VPO2 X X X X U
02
V
02
X X X X B2 B5 B2
VPO1 X X X X U
01
V
01
X X X X B1 B4 B1
VPO0 X X X X U
00
V
00
X X X X B0 B3 B0
Pixel
order Y
0123 0 1 0 1 note 5 note 6
Pixel
order UV
000 −−
Data rates LLC2 LLC2 LLC LLC2
I
2
C-bus
control
signals
OFTS0 = 0 OFTS0 = 1 OFTS0 = 1 OFTS0 = 0 OFTS0 = 0
OFTS1 = 1 OFTS1 = 0 OFTS1 = 1 OFTS1 = 0 OFTS1 = 0
RGB888 = X RGB888 = X RGB888 = X RGB888 = 0 RGB888 = 1

SAA7111AHZ/V4,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC VIDEO INPUT PROCESSOR 64-LQFP
Lifecycle:
New from this manufacturer.
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