LTC1068 Series
10
1068fc
PIN FUNCTIONS
Power Supply Pins
The V
+
and V
pins should each be bypassed with a
0.1µF capacitor to an adequate analog ground. The filters
power supplies should be isolated from other digital or
high voltage analog supplies. A low noise linear supply
is recommended. Using a switching power supply will
lower the signal-to-noise ratio of the filter. Figures 1 and 2
show typical connections for dual and single supply
operation.
Analog Ground Pin
The filters performance depends on the quality of the analog
signal ground. For either dual or single supply operation,
an analog ground plane surrounding the package is recom-
mended. The analog ground plane should be connected
to any digital ground at a single point. For single supply
operation, AGND should be bypassed to the analog ground
plane with at least a 0.47µF capacitor (Figure 2).
Two internal resistors bias the analog ground pin. For the
LTC1068, LTC1068-200 and LTC1068-25, the voltage at
the analog ground pin (AGND) for single supply is 0.5 × V
+
and for the LTC1068-50 it is 0.435 × V
+
.
Clock Input Pin
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source for
the device. The power supply for the clock source should
not be the filters power supply. The analog ground for the
filter should be connected to clock’s ground at a single
point only. Table 2 shows the clock’s low and high level
threshold values for dual or single supply operation.
Table 2. Clock Source High and Low Threshold Levels
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±5V ≥ 1.53V ≤ 0.53V
Single Supply = 5V ≥ 1.53V ≤ 0.53V
Single Supply = 3.3V ≥ 1.20V ≤ 0.53V
A pulsed generator can be used as a clock source provided
the high level ON time is at least 25% of the pulse period.
Sine waves are not recommended for clock input frequen-
cies less than 100kHz, since excessively slow clock rise
or fall times generate internal clock jitter (maximum clock
rise or fall time ≤ 1µs). The clock signal should be routed
from the right side of the IC package and perpendicular to
it to avoid coupling to any input or output analog signal
Figure 1. Dual Supply Ground Plane Connections Figure 2. Single Supply Ground Plane Connections
0.1µF
V
1068 F01
200Ω
DIGITAL GROUND
V
+
LTC1068
CLOCK
SOURCE
0.1µF
ANALOG
GROUND
PLANE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STAR
SYSTEM
GROUND
1068 F02
200Ω
DIGITAL GROUND
FOR MODE 3, THE S NODE
SHOULD BE TIED TO PIN 7 (AGND)
V
+
LTC1068
R
A
R
B
CLOCK
SOURCE
0.1µF
V
AGND
0.47µF
(1µF FOR
STOPBAND
FREQUENCIES
≤1kHz)
ANALOG
GROUND
PLANE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STAR
SYSTEM
GROUND
DEVICE
LTC1068
LTC1068-200
LTC1068-25
LTC1068-50
R
A
10k
11.3k
R
B
10k
8.6k
LTC1068 Series
11
1068fc
PIN FUNCTIONS
BLOCK DIAGRAM
path. A 200Ω resistor between clock source and Pin 11
will slow down the rise and fall times of the clock to further
reduce charge coupling (Figures 1 and 2).
Output Pins
Each 2nd order section of an LTC1068 device has three
outputs that typically source 17mA and sink 6mA. Driv-
ing coaxial cables or resistive loads less than 20k will
degrade the total harmonic distortion performance of
any filter design. When evaluating the distortion or noise
performance of a particular filter design implemented with
a LTC1068 device, the final output of the filter should be
buffered with a wideband, noninverting high slew rate
amplifier (Figure 3).
Inverting Input Pins
These pins are the inverting inputs of internal op amps
and are susceptible to stray capacitive coupling from low
impedance signal outputs and power supply lines.
In a printed circuit layout any signal trace, clock source
trace or power supply trace should be at least 0.1 inches
away from any inverting input pins
Summing Input Pins
These are voltage input pins. If used, they should be driven
with a source impedance below 5k. When they are not
used, they should be tied to the analog ground pin.
The summing pin connections determine the circuit to-
pology (mode) of each 2nd order section. Please refer to
Modes of Operation.
Figure 3. Wideband Buffer
+
LT
®
1354
1k
1068 F03
+
+
R
A
*
R
B
*
V
+
(8)
CLK (21)
V
(23)
NC (6)
NC (9)
NC (20)
NC (22)
AGND (7)
1068 BD
+
+ +
+
+
+
+
+
HPC/NC
(27)
BPC
(26)
LPC
(25)
HPB/NB
(2)
BPB
(3)
LPB
(4)
*THE RATIO R
A
/R
B
VARIES ±2%
BPA
(12)
LPA
(11)
INV A
(14)
AGND
(7)
INV C
(28)
HPA/NA
(13)
+
Σ
SA
(10)
+
+
+
+
INV D
(15)
INV B
(1)
HPD/ND
(16)
Σ
SB
(5)
Σ
SC
(24)
Σ
SD
(19)
+
+
BPD
(17)
LPD
(18)
PIN 28-LEAD SSOP PACKAGE
DEVICE
LTC1068
LTC1068-200
LTC1068-25
LTC1068-50
R
A
10k
11.3k
R
B
10k
8.6k
LTC1068 Series
12
1068fc
MODES OF OPERATION
Linear Technologys universal switched-capacitor filters
are designed for a fixed internal, nominal f
CLK
/f
O
ratio. The
f
CLK
/f
O
ratio is 100 for the LTC1068, 200 for the LTC1068-
200, 50 for the LTC1068-50 and 25 for the LTC1068-25.
Filter designs often require the f
CLK
/f
O
ratio of each section
to be different from the nominal ratio and in most cases
different from each other. Ratios other than the nominal
value are possible with external resistors. Operating modes
use external resistors, connected in different arrangements
to realize different f
CLK
/f
O
ratios. By choosing the proper
mode, the f
CLK
/f
O
ratio can be increased or decreased from
the part’s nominal ratio.
The choice of operating mode also effects the transfer
function at the HP/N pins. The LP and BP pins always give
the lowpass and bandpass transfer functions respectively,
regardless of the mode utilized. The HP/N pins have a
different transfer function depending on the mode used.
Mode 1 yields a notch transfer function. Mode 3 yields a
highpass transfer function. Mode 2 yields a highpass notch
transfer function (i.e., a highpass with a stopband notch).
More complex transfer functions, such as lowpass notch,
allpass or complex zeros, are achieved by summing two
or more of the LP, BP or HP/N outputs. This is illustrated
in sections Mode 2n and Mode 3a.
Choosing the proper mode(s) for a particular application
is not trivial and involves much more than just adjusting
the f
CLK
/f
O
ratio. Listed here are four of the nearly twenty
modes available. To make the design process simpler and
quicker, Linear Technology has developed the FilterCAD
for Widows design software. FilterCAD is an easy-to-use,
powerful and interactive filter design program. The de-
signer can enter a few filter specifications and the program
produces a full schematic. FilterCAD allows the designer
to concentrate on the filters transfer function and not get
bogged down in the details of the design. Alternatively,
those who have experience with the Linear Technology
family of parts can control all of the details themselves.
For a complete listing of all the operating modes, consult
the appendices of the FilterCAD manual or the Help files
in FilterCAD. FilterCAD can be obtained free of charge on
the Linear Technology web site (www.linear.com) or you
can order the FilterCAD CD-ROM by contacting Linear
Technology Marketing.
Mode 1
In Mode 1, the ratio of the external clock frequency to
the center frequency of each 2nd order section is inter-
nally fixed at the part’s nominal ratio. Figure 4 illustrates
Mode 1 providing 2nd order notch, lowpass and band-
pass outputs. Mode 1 can be used to make high order
Butterworth lowpass filters; it can also be used to make
low Q notches and for cascading 2nd order bandpass
functions tuned at the same center frequency. Mode 1 is
faster than Mode 3.
Please refer to the Operating Limits paragraph under Applica-
tions Information for a guide to the use of capacitor C
C
.
Mode 1b
Mode 1b is derived from Mode 1. In Mode 1b (Figure 5)
two additional resistors R5 and R6 are added to lower the
amount of voltage fed back from the lowpass output into
the input of the SA (or SB) switched-capacitor summer.
This allows the filters clock-to-center frequency ratio to
be adjusted beyond the part’s nominal ratio. Mode 1b
maintains the speed advantages of Mode 1 and should
be considered an optimum mode for high Q designs with
f
CLK
to f
CUTOFF
(or f
CENTER
) ratios greater than the part’s
nominal ratio.
The parallel combination of R5 and R6 should be kept
below 5k.
Please refer to the Operating Limits paragraph under Applica-
tions Information for a guide to the use of capacitor C
C
.
Figure 4. Mode 1, 2nd Order Filter Providing Notch,
Bandpassing and Lowpass Outputs
+
Σ
AGND
R1
N
BP
LP
V
IN
1068 F04
+
S
R2
R3
C
C
f
O
= ; f
n
= f
O
Q = ; H
ON
= – ; H
OBP
= –
H
OLP
= H
ON
R2
R1
R3
R1
R3
R2
f
CLK
RATIO
DEVICE
LTC1068
LTC1068-200
LTC1068-50
LTC1068-25
RATIO
100
200
50
25

LTC1068-200IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Active Filter Quad Universal Filter Building Block
Lifecycle:
New from this manufacturer.
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