1
FN8171.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9261
Single Supply/Low Power/256-Tap/SPI Bus
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer Single Supply
Device
• Wiper Resistance, 100 typical @ V
CC
= 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
•50k, 100k Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24 Ld SOIC, 24 Ld TSSOP
• Low Power CMOS
• Power Supply V
CC
= 5V ±10%
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9261 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
R
H0
R
L0
Bus
R
W0
Interface
and Control
V
CC
V
SS
SPI
Bus
Address
Data
Status
Write
Read
Transfer
50k or 100k versions
Inc/Dec
R
H1
R
L1
R
W1
Power-on Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
Interface
Control
Data Sheet October 12, 2006
O
B
S
O
L
E
T
E
P
RO
D
U
CT
P
O
S
S
I
B
L
E
S
U
BS
T
I
T
U
T
E
P
R
O
DU
C
T
I
S
L
2
2
4
2
4
