4
FN8171.4
October 12, 2006
HOLD (HOLD)
HOLD
is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD
must
be brought LOW while SCK is LOW. To resume
communication, HOLD
is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
D
EVICE ADDRESS (A1 - A0)
The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9261.
C
HIP SELECT (CS)
When CS
is HIGH, the X9261 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
LOW enables the X9261, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is
required prior to the start of any operation.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R
H
and
R
L
such that R
H0
and R
L0
are the terminals of POT 0
and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of R
W
such that R
W0
is the terminals of POT 0 and so on.
Supply Pins
S
YSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
G
ROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the system ground.
Other Pins
N
O CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
H
ARDWARE WRITE PROTECT INPUT (WP)
The WP
pin when LOW prevents nonvolatile writes to
the Data Registers.
PRINCIPLES OF OPERATION
Serial Interface
The X9261 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
must be
LOW and the HOLD
and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9261 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
Power-up and Down Requirements.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to
the potentiometer pins provided that V
CC
is always
more positive than or equal to V
H
, V
L
, and V
W
, i.e.,
V
CC
, V
H
, V
L
, V
W
. The V
CC
ramp rate specification is
always in effect.
X9261
