13
FN8171.4
October 12, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V
CC
and the voltages applied to the poten-
tiometer pins provided that V
CC
is always more positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
, V
W
. The
V
CC
power-up timing spec is always in effect.
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) t
PUR
and t
PUW
are the delays required from the time the (last) power supply (V
CC
-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
I
CC1
V
CC
supply current
(active)
400 Af
SCK
= 2.5 MHz, SO = Open, V
CC
= 6V
Other Inputs = V
SS
I
CC2
V
CC
supply current
(nonvolatile write)
15mAf
SCK
= 2.5MHz, SO = Open, V
CC
= 6V
Other Inputs = V
SS
I
SB
V
CC
current (standby) 5 ASCK = SI = V
SS
, Addr. = V
SS
,
CS
= V
CC
= 6V
I
LI
Input leakage current 10 AV
IN
= V
SS
to V
CC
I
LO
Output leakage current 10 AV
OUT
= V
SS
to V
CC
V
IH
Input HIGH voltage V
CC
x 0.7 V
CC
+ 1 V
V
IL
Input LOW voltage -1 V
CC
x 0.3 V
V
OL
Output LOW voltage 0.4 V I
OL
= 3mA
V
OH
Output HIGH voltage V
CC
- 0.8 V I
OH
= -1mA, V
CC
+3V
V
OH
Output HIGH voltage V
CC
- 0.4 V I
OH
= -0.4mA, V
CC
+3V
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
C
OUT
(6)
Output capacitance (SO) 8 pF V
OUT
= 0V
C
IN
(6)
Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK) 6 pF V
IN
= 0V
Symbol Parameter Min. Max. Units
t
r
V
CC
(6)
V
CC
Power-up rate 0.2 50 V/ms
t
PUR
(7)
Power-up to initiation of read operation 1 ms
Input Pulse Levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
X9261
14
FN8171.4
October 12, 2006
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
Symbol Parameter Min. Max. Units
f
SCK
SSI/SPI clock frequency 2 MHz
t
CYC
SSI/SPI clock cycle rime 500 ns
t
WH
SSI/SPI clock high rime 200 ns
t
WL
SSI/SPI clock low time 200 ns
t
LEAD
Lead time 250 ns
t
LAG
Lag time 250 ns
t
SU
SI, SCK, HOLD and CS input setup time 50 ns
t
H
SI, SCK, HOLD and CS input hold time 50 ns
t
RI
SI, SCK, HOLD and CS input rise time 2 s
t
FI
SI, SCK, HOLD and CS input fall time 2 s
t
DIS
SO output disable time 0 250 ns
t
V
SO output valid time 200 ns
t
HO
SO output hold time 0 ns
t
RO
SO output rise time 100 ns
t
FO
SO output fall time 100 ns
t
HOLD
HOLD time 400 ns
t
HSU
HOLD setup time 100 ns
t
HH
HOLD hold time 100 ns
t
HZ
HOLD low to output in high Z 100 ns
t
LZ
HOLD high to output in low Z 100 ns
T
I
Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
t
CS
CS deselect time 2 s
t
WPASU
WP, A0, A1 setup time 0 ns
t
WPAH
WP, A0, A1 hold time 0 ns
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macromodel
5V
1462
100pF
SO pin
2714
3V
1382
100pF
SO pin
1217
X9261
15
FN8171.4
October 12, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
TIMING DIAGRAMS
Input Timing
Symbol Parameter Typ. Max. Units
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
t
WRPO
Wiper response time after the third (last) power supply is stable 5 10 s
t
WRL
Wiper response time after instruction issued (all load instructions) 5 10 s
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
t
WH
X9261

X9261UV24-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC XDCP DUAL 256TAP 50K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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