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X9261UV24-2.7
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
16
FN8171.4
October 12, 2006
Output Timing
Hold Timing
XDCP Timing (for All Load Instructions)
Write Protect a
nd Device Address Pins
Timing
...
CS
SCK
SO
SI
ADDR
MSB
LSB
t
DIS
t
HO
t
V
...
...
CS
SCK
SO
SI
HOLD
t
HSU
t
HH
t
LZ
t
HZ
t
HOLD
t
RO
t
FO
...
CS
SCK
SI
MSB
LSB
VWx
t
WRL
...
SO
High Impedance
CS
WP
A0
A1
t
WP
ASU
t
WP
AH
(Any Instruction)
X9261
17
FN8171.4
October 12, 2006
APPLICATIONS INFORMATION
Basic Conf
igurations o
f Electroni
c Potentiome
ters
Application Circuits
V
R
RW
+V
R
I
Three terminal Potentiome
ter;
V
ariable voltage divider
T
wo terminal V
ariable Resistor;
V
ar
iable current
Noninverting Amplifie
r
V
olt
age Regulator
Offset V
oltage Adjustment
Co
mpa
rator with Hysterisis
+
–
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)
V
IN
317
+
–
V
S
V
O
R
2
R
1
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
V
LL
= {R
1
/(R
1
+R
2
)} V
O
(min)
100k
10k
10k
10k
-12V
+12V
TL072
+
–
V
S
V
O
R
2
R
1
}
}
X9261
18
FN8171.4
October 12, 2006
Application Circuits (continued)
Attenuator
Filter
Inverting Amplifier
Equivalent L-R Circuit
+
–
V
S
V
O
R
3
R
1
V
O
= G V
S
-1/2
G
+1/2
G
O
= 1 + R
2
/R
1
fc = 1/(2
RC)
+
–
V
S
V
O
R
2
R
1
Z
IN
= R
2
+ s R
2
(R
1
+ R
3
) C
1
= R
2
+ s Leq
(
R
1
+ R
3
) >> R
2
+
–
V
S
Function Generator
R
2
R
4
R
1
= R
2
= R
3
= R
4
= 10k
+
–
V
S
R
2
R
1
R
C
}
}
V
O
= G V
S
G = - R
2
/R
1
R
2
C
1
R
1
R
3
Z
IN
+
–
R
2
+
–
R
1
}
}
R
A
R
B
frequency
R
1
, R
2
, C
amplitude
R
A
, R
B
C
V
O
X9261
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
X9261UV24-2.7
Mfr. #:
Buy X9261UV24-2.7
Manufacturer:
Renesas / Intersil
Description:
IC XDCP DUAL 256TAP 50K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
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