AX5031-1-TW30 Datasheet AX5031-1-TW30, MOD5031-868-2-GEVB, AX5031-1-TA05 | P10-P12

AX5031

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CIRCUIT DESCRIPTION

The AX5031 is a true single chip low−power CMOS

transmitter primarily for use in SRD bands. The on−chip

transmitter consists of a fully integrated RF front−end with

modulator, and demodulator. Base band data processing is

implemented in an advanced and flexible communication

controller that enables user friendly communication via the

SPI interface.

AX5031 can be operated from a 2.2 V to 3.6 V power

supply over a temperature range of −40°C to 85°C, it

consumes 11 − 45 mA for transmitting, depending on the

output power.

The AX5031 features make it an ideal interface for

integration into various battery powered SRD solutions such

as ticketing or as transmitter for telemetric applications e.g.

in sensors. As primary application, the transmitter is

intended for UHF radio equipment in accordance with the

European Telecommunication Standard Institute (ETSI)

specification EN 300 220−1 and the US Federal

Communications Commission (FCC) standard CFR47, part

15. The use of AX5031 in accordance to FCC Par 15.247,

allows for improved range in the 915 MHz band.

Additionally AX5031 is compatible with the low frequency

standards of 802.15.4 (ZigBee).

The AX5031 receives data via the SPI port in frames. This

standard operation mode is called Frame Mode. Pre and post

ambles as well as checksums can be generated

automatically. Interrupts control the data flow between a

controller and the AX5031.

The AX5031 behaves as a SPI slave interface.

Configuration of the AX5031 is also done via the SPI

interface.

AX5031 supports any data rate from 1 kbps to 350 kbps

for FSK and MSK, from 1 kbps to 2000 kbps for ASK and

from 10 kbps to 2000 kbps for PSK. To achieve optimum

performance for specific data rates and modulation schemes

several register settings to configure the AX5031 are

necessary, they are outlined in the following, for details see

the AX5031 Programming Manual.

Spreading is possible on all data rates and modulation

schemes. The net transfer rate is reduced by a factor of 15 in

this case. For ZigBee either 600 or 300 kbps modes have to

be chosen.

Voltage Regulator

The AX5031 uses an on−chip voltage regulator to create

a stable supply voltage for the internal circuitry at pin VREG

from the primary supply VDD_IO. All VDD pins of the

device must be connected to VREG. The antenna pins

ANTP and ANTN must be DC biased to VREG. The I/O

level of the digital pins is VDD_IO.

The voltage regulator requires a 1 mF low ESR capacitor

at pin VREG.

In power−down mode the voltage regulator typically

outputs 1.7 V at VREG, if it is powered−up its output rises

to typically 2.5 V. At device power−up the regulator is in

power−down mode.

The voltage regulator must be powered−up before

transmit operations can be initiated. This is handled

automatically when programming the device modes via the

PWRMODE register.

check if the regulated voltage is above 1.3 V or 2.3 V, sticky

versions of the bits are provided that can be used to detect

low power events (brown−out detection).

Crystal Oscillator

The on−chip crystal oscillator allows the use of an

inexpensive quartz crystal as the RF generation subsystem’s

timing reference. Although a wider range of crystal

frequencies can be handled by the crystal oscillator circuit,

it is recommended to use 16 MHz as reference frequency for

ASK and PSK modulations independent of the data rate. For

FSK it is recommended to use a 16 MHz crystal for data rates

below 200 kbps and 24 MHz for data rates above 200 kbps.

The oscillator circuit is enabled by programming the

PWRMODE register. At power−up it is not enabled.

To adjust the circuit’s characteristics to the quartz crystal

being used without using additional external components,

both the transconductance and the tuning capacitance of the

crystal oscillator can be programmed.

The transconductance is programmed via register bits

XTALOSCGM[3:0] in register XTALOSC.

The integrated programmable tuning capacitor bank

makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external

capacitors. It is programmed using bits XTALCAP[5:0] in

SYSCLK Output

The SYSCLK pin outputs the reference clock signal

divided by a programmable integer. Divisions from 1 to

2048 are possible. For divider ratios > 1 the duty cycle is

50%. Bits SYSCLK[3:0] in the PINCFG1 register set the

divider ratio. The SYSCLK output can be disabled.

Power−on−reset (POR)

AX5031 has an integrated power−on−reset block. No

external POR circuit or signal is required.

After POR the AX5031 can be reset by SPI accesses, this

is achieved by toggling the bit RST in the PWRMODE

After POR or reset all registers are set to their default

values.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a

fully integrated synthesizer, which multiplies the reference

frequency from the crystal oscillator to get the desired RF

frequency. The advanced architecture of the synthesizer

AX5031

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enables frequency resolutions of 1 Hz, as well as fast settling

times of 5 – 50 ms depending on the settings (see section:

AC Characteristics). Fast settling times mean fast start−up,

which enables low−power system design.

The frequency must be programmed to the desired carrier

frequency.

The synthesizer loop bandwidth can be programmed, this

serves three purposes:

1. Start−up time optimization, start−up is faster for

higher synthesizer loop bandwidths.

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths.

3. Adaptation of the bandwidth to the data−rate. For

transmission of FSK and MSK it is required that

the synthesizer bandwidth must be in the order of

the data−rate.

VCO

An on−chip VCO converts the control voltage generated

by the charge pump and loop filter into an output frequency.

The frequency can be programmed in 1 Hz steps in the

FREQ or FREQB registers. To chose FREQB setting rather

than FREQ, the bit FREQSEL in register PLLLOOP must

be set. For operation in the 433 MHz band, the BANDSEL

bit in the PLLLOOP register must be programmed.

VCO Auto−Ranging

The AX5031 has an integrated auto−ranging function,

which allows to set the correct VCO range for specific

frequency generation subsystem settings automatically.

Typically it has to be executed after power−up. The function

is initiated by setting the RNG_START bit in the

PLLRANGING register. The bit is readable and a 0 indicates

the end of the ranging process. The RNGERR bit indicates

the correct execution of the auto−ranging.

Loop Filter and Charge Pump

The AX5031 internal loop filter configuration together

with the charge pump current sets the synthesizer loop band

width. The loop−filter has three configurations that can be

programmed via the register bits FLT[1:0] in register

PLLLOOP, the charge pump current can be programmed

using register bits PLLCPI[1:0] also in register PLLLOOP.

Synthesizer bandwidths are typically 50 – 500 kHz

depending on the PLLLOOP settings, for details see the

section: AC Characteristics.

Registers

Table 10. REGISTERS

PLLLOOP

FREQSEL Switches between carrier frequencies defined by FREQ and FREQB.

Using this feature allows to avoid glitches in the PLL output frequency caused by serially

changing the 4 bytes required to set a carrier frequency.

FLT[1:0] Synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster

settling time, bandwidth increases of factor 2 and 5 are possible.

PLLCPI[2:0] Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and

improve the phase−noise) for low data−rate transmissions.

BANDSEL Switches between 868 MHz / 915 MHz and 433 MHz bands

FREQ Programming of the carrier frequency

FREQB Programming of the 2

carrier frequency, switch to this carrier frequency by setting bit

FREQSEL = 1.

PLLRANGING Initiate VCO auto−ranging and check results

RF Output Stage (ANTP/ANTN)

The AX5031 uses fully differential antenna pins.

The PA drives the signal generated by the frequency

generation subsystem out to the differential antenna

terminals. The output power of the PA is programmed via

bits TXRNG[3:0] in the register TXPWR. Output power as

well as harmonic content will depend on the external

impedance seen by the PA, recommendations are given in

the section Application Information.

Encoder

The encoder is located between the Framing Unit and the

Modulator. It can optionally transform the bit−stream in the

following ways:

• It can invert the bit stream.

• It can perform differential encoding. This means that a

zero is transmitted as no change in the level, and a one

is transmitted as a change in the level. Differential

encoding is useful for PSK, because PSK transmissions

can be received either as transmitted or inverted, due to

the uncertainty of the initial phase. Differential

encoding / decoding removes this uncertainty.

• It can perform Manchester encoding. Manchester

encoding ensures that the modulation has no DC

content and enough transitions (changes from 0 to 1 and

from 1 to 0) for the demodulator bit timing recovery to

function correctly, but does so at a doubling of the data

rate.

AX5031

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• It can perform Spectral Shaping. Spectral Shaping

removes DC content of the bit stream, ensures

transitions for the demodulator bit timing recovery, and

makes sure that the transmitted spectrum does not have

discrete lines even if the transmitted data is cyclic. It

does so without adding additional bits, i.e. without

changing the data rate. Spectral Shaping uses a self

synchronizing feedback shift register.

The encoder is programmed using the register

ENCODING, details and recommendations on usage are

given in the AX5031 Programming Manual.

Framing and FIFO

Most radio systems today group data into packets. The

framing unit is responsible for converting these packets into

a bit−stream suitable for the modulator.

The Framing unit supports three different modes:

• HDLC

• Raw

• 802.15.4 compliant

The micro−controller communicates with the framing

unit through a 32 level y 10 bit FIFO. The FIFO decouples

micro−controller timing from the radio (modulator) timing.

The bottom 8 bits of the FIFO contain transmit data. The top

2 bit are used to convey meta information in HDLC and

802.15.4 modes. They are unused in Raw mode. The meta

information consists of packet begin / end information and

the result of CRC checks. The FIFO can be written in

power−down mode.

The FIFO can be operated in polled or interrupt driven

modes. In polled mode, the micro−controller must

periodically read the FIFO status register or the FIFO count

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT

FULL and programmable level interrupts are provided. The

AX5031 signals interrupts by asserting (driving high) its

IRQ line. The interrupt line is level triggered, active high.

Interrupts are acknowledged by removing the cause for the

interrupt, i.e. by emptying or filling the FIFO.

Basic FIFO status (EMPTY, FULL, Overrun, Underrun,

and the top two bits of the top FIFO word) are also provided

during each SPI access on MISO while the micro−controller

shifts out the register address on MOSI. See the SPI interface

section for details. This feature significantly reduces the

number of SPI accesses necessary.

HDLC Mode

NOTE: HDLC mode follows High−Level Data Link

Control (HDLC, ISO 13239) protocol.

HDLC Mode is the main framing mode of the AX5031. In

this mode, the AX5031 performs automatic packet

delimiting, and optional packet correctness check by

inserting and checking a cyclic redundancy check (CRC)

field.

The packet structure is given in the following table.

Table 11.

Flag Address Control Information FCS (Optional Flag)

8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit

HDLC packets are delimited with flag sequences of

content 0x7E.

In AX5031 the meaning of address and control is user

defined. The Frame Check Sequence (FCS) can be

programmed to be CRC−CCITT, CRC−16 or CRC−32.

For details on implementing a HDLC communication see

the AX5031 Programming Manual.

Raw Mode

In Raw mode, the AX5031 does not perform any packet

delimiting or byte synchronization. It simply serialises

transmit bytes.

This mode is ideal for implementing legacy protocols in

software.

802.15.4 (ZigBee)

802.15.4 uses binary phase shift keying (PSK) with 300

kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on the

radio. The usable bit rate is only a 15

of the radio bit rate,

however. A spreading function in the transmitter expands

the user bit rate by a factor of 15, to make the transmission

more robust.

In 802.15.4 mode, the AX5031 framing unit performs the

spreading according to the 802.15.4 specification.

The 802.15.4 is a universal DSSS mode, which can be

used with any modulation or data rate as long as it does not

violate the maximum data rate of the modulation being used.

Therefore the maximum DSSS data rate is 16 kbps for FSK

and 40 kbps for ASK and PSK.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

AX5031-1-TW30

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RF Transmitter RADIO TRANSMITTER

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AX5031-1-TW30

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