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19
QFN20 PACKAGE INFORMATION
QFN20 4x4, 0.5P
CASE 485BH
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
D
E
B
C0.15
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
K
D2
E2
C
C0.15
C0.10
C0.08
A1
SEATING
PLANE
e
20X
NOTE 3
b
20X
0.10 C
0.05 C
A
BB
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 −−− 0.05
b 0.20 0.30
D 4.00 BSC
D2 2.60 2.80
E 4.00 BSC
E2 2.60 2.80
e 0.50 BSC
K 0.20 −−−
L 0.35 0.45
6
11
16
20X
0.50
PITCH
4.30
0.60
4.30
DIMENSIONS: MILLIMETERS
0.35
20X
1
L
A3 0.20 REF
MOUNTING FOOTPRINT
NOTE 4
A3
DETAIL B
2.80
2.80
1
PACKAGE
OUTLINE
DETAIL A
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
L1 0.00 0.15
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20
QFN Soldering Profile
Figure 6. QFN Soldering Profile
Preheat Reflow Cooling
T
P
T
L
T
sMAX
T
sMIN
t
s
t
L
t
P
T
25
°
C
to
Peak
Temperature
Time
25°C
Table 19.
Profile Feature PbFree Process
Average RampUp Rate 3°C/s max.
Preheat Preheat
Temperature Min T
sMIN
150°C
Temperature Max T
sMAX
200°C
Time (T
sMIN
to T
sMAX
) t
s
60 – 180 sec
Time 25°C to Peak Temperature T
25
°
C
to
Peak
8 min max.
Reflow Phase
Liquidus Temperature T
L
217°C
Time over Liquidus Temperature t
L
60 – 150 s
Peak Temperature t
p
260°C
Time within 5°C of actual Peak Temperature T
p
20 – 40 s
Cooling Phase
Rampdown rate 6°C/s max.
1. All temperatures refer to the top side of the package, measured on the the package body surface.
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21
QFN Recommended Pad Layout
1. PCB land and solder masking recommendations
are shown in Figure 7.
Figure 7. PCB Land and Solder Mask Recommendations
A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum
B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum
C = Clearance from PCB land edge to solder mask opening to be as tight as possible
to ensure that some solder mask remains between PCB pads.
D = PCB land length = QFN solder pad length + 0.1 mm
E = PCB land width = QFN solder pad width + 0.1 mm
2. Thermal vias should be used on the PCB thermal
pad (middle ground pad) to improve thermal
conductivity from the device to a copper ground
plane area on the reverse side of the printed circuit
board. The number of vias depends on the package
thermal requirements, as determined by thermal
simulation or actual testing.
3. Increasing the number of vias through the printed
circuit board will improve the thermal
conductivity to the reverse side ground plane and
external heat sink. In general, adding more metal
through the PC board under the IC will improve
operational heat transfer, but will require careful
attention to uniform heating of the board during
assembly.
Assembly Process
Stencil Design & Solder Paste Application
1. Stainless steel stencils are recommended for solder
paste application.
2. A stencil thickness of 0.125 – 0.150 mm
(5 – 6 mils) is recommended for screening.
3. For the PCB thermal pad, solder paste should be
printed on the PCB by designing a stencil with an
array of smaller openings that sum to 50% of the
QFN exposed pad area. Solder paste should be
applied through an array of squares (or circles) as
shown in Figure 8.
4. The aperture opening for the signal pads should be
between 5080% of the QFN pad area as shown in
Figure 9.
5. Optionally, for better solder paste release, the
aperture walls should be trapezoidal and the
corners rounded.
6. The fine pitch of the IC leads requires accurate
alignment of the stencil and the printed circuit
board. The stencil and printed circuit assembly
should be aligned to within + 1 mil prior to
application of the solder paste.
7. Noclean flux is recommended since flux from
underneath the thermal pad will be difficult to
clean if watersoluble flux is used.
Figure 8. Solder Paste Application on Exposed Pad

AX5031-1-TW30

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
RF Transmitter RADIO TRANSMITTER
Lifecycle:
New from this manufacturer.
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