AX5031
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16
Table 17. CONTROL REGISTER MAP
Addr Description
Bit
ResetDirNameAddr Description
01234567
ResetDirName
22 FREQ1 RW 11001100 FREQ(15:8) Synthesizer Frequency
23 FREQ0 RW 11001101 FREQ(7:0) Synthesizer Frequency
25 FSKDEV2 RW 00000010 FSKDEV(23:16) FSK Frequency Deviation
26 FSKDEV1 RW 01100110 FSKDEV(15:8) FSK Frequency Deviation
27 FSKDEV0 RW 01100110 FSKDEV(7:0) FSK Frequency Deviation
2C PLLLOOP RW 00011101 FREQS
EL
reserved BANDSEL PLLCPI(2:0) FLT(1:0) Synthesizer Loop Filter
Settings
2D PLLRANGING RW 00001000 STICKY
LOCK
PLL
LOCK
RNGERR RNG
START
VCOR(3:0) Synthesizer VCO
AutoRanging
Transmitter
30
TXPWR RW −−−−1000 TXRNG(3:0) Transmit Power
31 TXRATEHI RW 00001001 TXRATE(23:16) Transmitter Bitrate
32 TXRATEMID RW 10011001 TXRATE(15:8) Transmitter Bitrate
33 TXRATELO RW 10011010 TXRATE(7:0) Transmitter Bitrate
34 MODMISC RW ––––––11 reserved PTTLCK
GATE
Misc RF Flags
FIFO, Part 2
35
FIFOCOUNT R −−000000 FIFOCOUNT(5:0) FIFO Fill state
36 FIFOTHRESH RW −−000000 FIFOTHRESH(5:0) FIFO Threshold
37 FIFOCONTROL
2
RW 0−−−−−00 CLEAR STOPONERR
(1:0)
Additional FIFO control
Crystal Oscillator, Part 2
4F
XTALCAP RW −−000000 XTALCAP(5:0) Crystal oscillator tuning
capacitance
4FSK Control
50
FOURFSK RW −−−−−−−0 FOURFSKENA 4FSK Control
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APPLICATION INFORMATION
Typical Application Diagram
Figure 4. Typical Application Diagram
VDD
ANTP
ANTN
VDD
VREG
CLK16N
MOSI
IRQ
VDD_IO
AX5031
VREG
GND
ANTENNA
TO/FROM MICROCONTROLLER
From Power Supply
MISO
CLK16P
1 mF
CLK
SEL
SYSCLK
The GND connection to AX5031 is made via the exposed
center pad of the QFN package. It is mandatory to connect
this pad to GND.
It is mandatory to add 1 mF (low ESR) between VREG and
GND. Decoupling capacitors are not all drawn. It is
recommended to add 100 nF decoupling capacitor for every
VDD and VDD_IO pin. In order to reduce noise on the
antenna inputs it is recommended to add 27 pF on the VDD
pins close to the antenna interface.
AX5031
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Antenna Interface Circuitry
A small antenna can be directly connected to the AX5031
ANTP and ANTN pins with an optional translation network.
The network must provide DC power to the PA. A biasing
to VREG is necessary.
Beside biasing and impedance matching, the proposed
network also provides low pass filtering to limit spurious
emission.
Singleended Antenna Interface
Figure 5. Structure of the Antenna Interface to 50 W Singleended Equipment or Antenna
CC1
CB1
LT2
IC Antenna
Pins
VRE
G
VREG
LT1
LC2
LC1
CM1
LB1
CB2
LB2
CF1
CF2
LF1
CT1
CT2
CC2
CM2
50 W singleended
equipment or
antenna
Optional filter stage
to suppress TX
harmonics
Table 18.
Frequency Band
LC1,2
[nH]
CC1,2
[pF]
LT1,2
[nH]
CT1,2
[pF]
CM1,2
[pF]
LB1,2
[nH]
CB1,2
[pF]
LF1
[nH]
CF1,2
[pF]
868 / 915 MHz 68 1.2 12 18 2.4 12 2.7
0 W
NC
433 MHz 120 2.7 39 7.5 6.0 27 5.2
0 W
NC
Voltage Regulator
The AX5031 has an integrated voltage regulator which
generates a stable supply voltage VREG from the voltage
applied at VDD_IO. Use VREG to supply all the VDD
supply pins.

AX5031-1-TW30

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
RF Transmitter RADIO TRANSMITTER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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