AX5031-1-TW30 Datasheet AX5031-1-TW30, MOD5031-868-2-GEVB, AX5031-1-TA05 | P13-P15

AX5031

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Modulator

Depending on the transmitter settings the modulator

generates various inputs for the PA:

Table 12.

Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate

ASK PA off PA on BW = BITRATE 2000 kBit/s

FSK/MSK/GFSK

Df = −f

deviation

Df = +f

deviation

BW = (1 + h) ⋅BITRATE 350 kBit/s

PSK

DF = 0° DF = 180°

BW = BITRATE 2000 kBit/s

h = modulation index. It is the ratio of the

deviation compared to the bit−rate;

deviation

= 0.5⋅h⋅BITRATE

ASK = amplitude shift keying

FSK = frequency shift keying

MSK = minimum shift keying; MSK is a special case

of FSK, where h = 0.5, and therefore

deviation

= 0.25⋅BITRATE; the advantage of

MSK over FSK is that it can be demodulated

more robustly.

PSK = phase shift keying

OQPSK = offset quadrature shift keying. The AX5031

supports OQPSK. However, unless

compatibility to an existing system is required,

MSK should be preferred.

4−FSK = four frequencies are used to transmit two bits

simultaneously during each symbol

Table 13.

Modulation Symbol = 00 Symbol = 01 Symbol = 10 Symbol = 11 Max. Bitrate

4−FSK

Df = −3⋅f

deviation

Df = −f

deviation

Df = +f

deviation

Df = +3⋅f

deviation

400 kBit/s

All modulation schemes are binary.

PWRMODE Register

The PWRMODE register controls, which parts of the chip are operating.

Table 14. PWRMODE REGISTER

PWRMODE Register Name Description Typical Idd

0000 POWERDOWN All digital and analog functions, except the register file, are disabled. The

core supply voltage is reduced to conserve leakage power. SPI registers

are still accessible, but at a slower speed. FIFO access is possible.

0.25 mA

0100 VREGON All digital and analog functions, except the register file, are disabled. The

core voltage, however is at its nominal value for operation, and all SPI

registers are accessible at the maximum speed.

140 mA

0101 STANDBY The crystal oscillator is powered on; the transmitter is off.

500 mA

1100 SYNTHTX The synthesizer is running on the transmit frequency. The transmitter is still

off. This mode is used to let the synthesizer settle on the correct frequency

for transmit.

10 mA

1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode

before the synthesizer has completely settled on the transmit frequency (in

SYNTHTX mode), otherwise spurious spectral transmissions will occur.

11 − 45 mA

Table 15. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION

Step PWRMODE Remarks

1 POWERDOWN

2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.

4 SYNTHTX

The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics

3 FULLTX Data transmission

4 POWERDOWN

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Serial Peripheral Interface

The AX5031 can be programmed via a four wire serial

interface according SPI using the pins CLK, MOSI, MISO

and SEL. Registers for setting up the AX5031 are

programmed via the serial peripheral interface in all device

modes.

When the interface signal SEL is pulled low, a 16 bit

configuration data stream is expected on the input signal pin

MOSI, which is interpreted as D0...D7, A0...A6, R_N/W.

Data read from the interface appears on MISO.

Figure 6 shows a write/read access to the interface. The

data stream is built of an address byte including read/write

information and a data byte. Depending on the R_N/W bit

and address bits A[6..0], data D[7..0] can be written via

MOSI or read at the pin MISO.

R_N/W = 0 means read mode, R_N/W = 1 means write

mode.

The read sequence starts with 7 bits of status information

S[6..0] followed by 8 data bits.

The status bits contain the following information:

Table 16.

S6 S5 S4 S3 S2 S1 S0

PLL LOCK FIFO OVER FIFO UNDER FIFO FULL FIFO EMPTY FIFOSTAT(1) FIFOSTAT(0)

SPI Timing

Figure 3. Serial Peripheral Interface Timing

Tsh

R/ W

SCK

MOSI

MISO

A6 A5 A4 A3 A2 A1

A0 D6 D5 D4 D0D1D2D3

D7 D6 D5 D4 D3 D2

D0S6 S5 S4 S3 S2 S1 S0

Tssd Tco

Tss Tck TchTcl ThTs

Tssz

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This section describes the bits of the register bank in

detail. The registers are grouped by functional block to

facilitate programming.

No checks are made whether the programmed

combination of bits makes sense! Bit 0 is always the LSB.

NOTES: Whole registers or register bits marked as

reserved should be kept at their default values.

All addresses not documented here must not be

accessed, neither in reading nor in writing.

Table 17. CONTROL REGISTER MAP

Addr Name Dir Reset

Bit

Description

7 6 5 4 3 2 1 0

Revision & Interface Probing

REVISION R 00100001 SILICONREV(7:0) Silicon Revision

1 SCRATCH RW 11000101 SCRATCH(7:0) Scratch Register

Operating Mode

PWRMODE RW 011−0000 RST REFEN XOEN − PWRMODE(3:0) Power Mode

Crystal Oscillator, Part 1

XTALOSC RW −−−−0010 − − − − XTALOSCGM(3:0) GM of Crystal Oscillator

FIFO, Part 1

FIFOCTRL RW −−−−−−11 FIFOSTAT(1:0) FIFO

OVER

FIFO

UNDER

FIFO

FULL

FIFO

EMPTY

FIFOCMD(1:0) FIFO Control

5 FIFODATA RW −−−−−−−− FIFODATA(7:0) FIFO Data

Interrupt Control

IRQMASK RW −0000000 − IRQMASK(6:0) IRQ Mask

7 IRQREQUEST R −−−−−−−− − IRQREQUEST(6:0) IRQ Request

Interface & Pin Control

PINCFG1 RW 00101000 − IRQZ − SYSCLK(3:0) Pin Configuration 1

0D PINCFG2 RW 00000000 − IRQE − − IRQI − Pin Configuration 2

0E PINCFG3 RW 0−−−−−−− reserved − − SYSCLKR − IRQR − Pin Configuration 3

0F IRQINVERSION RW −0000000 − IRQINVERSION(6:0) IRQ Inversion

Modulation & Framing

MODULATION RW −0000010 − MODULATION(6:0) Modulation

11 ENCODING RW −−−00010 − − − ENC

NOSYNC

ENC

MANCH

ENC

SCRAM

ENC

DIFF

ENC

INV

Encoder/Decoder

Settings

12 FRAMING RW −0000000 − HSUPP CRCMODE(1:0) FRMMODE(2:0) − Framing settings

14 CRCINIT3 RW 11111111 CRCINIT(31:24) CRC Initialization Data or

Preamble

15 CRCINIT2 RW 11111111 CRCINIT(23:16) CRC Initialization Data or

Preamble

16 CRCINIT1 RW 11111111 CRCINIT(15:8) CRC Initialization Data or

Preamble

17 CRCINIT0 RW 11111111 CRCINIT(7:0) CRC Initialization Data or

Preamble

Voltage Regulator

VREG R −−−−−−−− − − − − SSDS SSREG SDS SREG Voltage Regulator Status

Synthesizer

FREQB3 RW 00111001 FREQB(31:24) 2

Synthesizer Frequency

1D FREQB2 RW 00110100 FREQB(23:16) 2

Synthesizer Frequency

1E FREQB1 RW 11001100 FREQB(15:8) 2

Synthesizer Frequency

1F FREQB0 RW 11001101 FREQB(7:0) 2

Synthesizer Frequency

20 FREQ3 RW 00111001 FREQ(31:24) Synthesizer Frequency

21 FREQ2 RW 00110100 FREQ(23:16) Synthesizer Frequency

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

AX5031-1-TW30

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Manufacturer:

ON Semiconductor

Description:

RF Transmitter RADIO TRANSMITTER

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AX5031-1-TW30

AX5031-1-TW30

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