Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps
Burst Mode Clock and Data Recovery IC with Deserializer
Data Sheet
ADN2855
Rev. B Document Feedback
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FEATURES
Serial data input
155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps
12-bit acquisition time
4-bit parallel LVDS output interface
Patented dual-loop clock recovery architecture
Integrated PRBS generator
Byte rate reference clock
Loss-of-lock indicator
Supports double data rate (DDR)-compatible FPGA
I
2
C interface to access optional features
Single-supply operation: 3.3 V
Power
670 mW typical in serial output mode
825 mW typical in deserializer mode
5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
Passive optical networks
GPON/BPON/GEPON OLT receivers
GENERAL DESCRIPTION
The ADN2855 is a burst mode clock and data recovery IC
designed for GPON/BPON/GEPON optical line terminal (OLT)
receiver applications. The part can operate at 155.52 Mbps,
622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable
via the I
2
C interface.
The ADN2855 frequency locks to the OLT reference clock and
aligns to the input data within 12 bits of the start of the preamble.
The device provides a full rate or an optional half rate output
clock for a double data rate (DDR) interface to an FPGA or
digital ASIC.
All specifications are quoted for −40°C to +85°C ambient tempera-
ture, unless otherwise noted. The ADN2855 is available in a
compact 5 mm × 5 mm, 32-lead chip scale package.
FUNCTIONAL BLOCK DIAGRAM
2
RESET
DATAV
DATxP,
DATxN
2
VCC VEE
SDA
SCK
CF1 CF2
PIN
NIN
CML INPUT
BUFFER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY/
LOCK
DETECT
D
ATA
RE-TIMING
DIVIDER
I
2
C
DESERIALIZER
LOOP
FI
LTER
LOOP
FIL
TER
4 × 2
REFCLK
P,
REFCLKN
06660-001
CLKOUTP
,
CLKOUTN
SQUELCH
ADN2855
Figure 1.
ADN2855* PRODUCT PAGE QUICK LINKS
Last Content Update: 04/10/2017
COMPARABLE PARTS
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EVALUATION KITS
ADN2855 Evaluation Board
DOCUMENTATION
Data Sheet
ADN2855: Multirate 155 Mbps/622 Mbps/1244 Mbps/
1250 Mbps Burst Mode Clock and Data Recovery IC with
Deserializer Data Sheet
DESIGN RESOURCES
ADN2855 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADN2855 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Jitter Specifications ....................................................................... 3
Output and Timing Specifications ............................................. 4
Timing Characteristcs .................................................................. 5
Reset Timing Options .................................................................. 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
I
2
C Interface Timing and Internal Register Description ..............9
Theory of Operation ...................................................................... 11
Functional Description .................................................................. 12
Frequency Acquisition ............................................................... 12
Squelch Mode ............................................................................. 12
I
2
C Interface ................................................................................ 12
Reference Clock .......................................................................... 13
Output Modes ............................................................................. 14
Disable Output Buffers .............................................................. 14
Applications Information .............................................................. 15
PCB Design Guidelines ............................................................. 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changed CP-32-13 to CP-32-20 .................................. Throughout
Changes to Soldering Guidelines for Chip Scale Package
Section ........................................................................................................ 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/2013—Rev. 0 to Rev. A
Change to Table 5 ............................................................................. 7
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
1/2009—Revision 0: Initial Version

ADN2855ACPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products BDR
Lifecycle:
New from this manufacturer.
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