ADN2855ACPZ-R7 Datasheet ADN2855ACPZ-R7, ADN2855ACPZ, ADN2855XCPZ | P13-P15

ADN2855 Data Sheet

Rev. B | Page 12 of 20

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2855 operates in burst data recovery mode, which

requires the use of the OLT system reference clock as an acqui-

sition aid. The ADN2855 acquires frequency with respect to

this reference clock, which is frequency locked to the incoming

burst of data from the ONT.

The ADN2855 must be placed in lock to reference clock mode

by setting CTRLA[0] = 1. A frequency acquisition is then initiated

by writing a 1 to 0 transition into CTRLB[5]. This must be done

well before the ADN2855 is expected to lock to an incoming

burst, preferably right after power-up and once there is a valid

reference clock being supplied to the device. As long as the

reference clock to the ADN2855 is always present, this frequency

acquisition needs to take place only once. It does not need to be

repeated between bursts of data in its normal operating mode.

The initial frequency acquisition with respect to the reference

clock takes ~10 ms.

To lock to burst data, a RESET signal must be asserted following

a previous burst (or at startup) according to the timing diagrams

shown in the Reset Timing Options section. The RESET signal

must be deasserted prior to the 1010… portion of the preamble.

The ADN2855 uses a preamble detector that identifies the 1010…

portion of the preamble and quickly acquires the phase of the

incoming burst within 12 UI.

The frequency loop requires a single external capacitor between

Pin 14, CF2, and Pin 15, CF1. A 0.47 µF ± 20%, X7R ceramic

chip capacitor with <10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 µF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 μF capacitor should be greater than 300 MΩ.

DATAV

Operation

The ADN2855 has a data valid indicator that asserts when the

ADN2855 acquires the phase of the maximum transition

density portion of the preamble. This takes 12 UI from the start

of the 1010… pattern in the preamble. The

DATAV

output

remains asserted until the RESET signal is asserted following

the end of the current burst of data, at which point the

DATAV

output deasserts. The

DATAV

output is active low and is

LVTTL compatible.

SQUELCH MODE

When the squelch input, Pin 30, is driven to a TTL high state,

both the clock and data outputs are set to the zero state to

suppress downstream processing. If the squelch function is not

required, Pin 30 should be tied to VEE.

If it is desired that the DATxP/DATxN and CLKOUTP/

CLKOUN outputs be squelched while the output data is

invalid, then the

DATAV

pin can be hardwired directly to

the SQUELCH input.

C INTERFACE

The ADN2855 supports a 2-wire, I

C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices con-

nected to the bus. Each slave device is recognized by a unique

address. The ADN2855 has four possible 7-bit slave addresses

for both read and write operations. The MSB of the 7-bit slave

address, SADDR[7] is factory programmed to 1. Bit 2 of the slave

address, SADDR[2], is set by Pin 1. Bit 1 of the slave address,

SADDR[1], is set by Pin 3. Slave Address Bits[6:3] are defaulted

to all 0s. The slave address consists of the seven MSBs of an 8-bit

word. The LSB of the word, SADDR[0], sets either a read or

write operation (see Figure 10). Logic 1 corresponds to a read

operation, and Logic 0 corresponds to a write operation.

To control the device on the bus, use the following protocol.

First, the master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while SCK

remains high. This indicates that an address/data stream

follows. All peripherals respond to the start condition and shift

the next eight bits (the 7-bit address and the R/W bit). The bits

are transferred from MSB to LSB. The peripheral that recognizes

the transmitted address responds by pulling the data line low

during the ninth clock pulse. This is known as an acknowledge

bit. All other devices withdraw from the bus at this point and

maintain an idle condition. The idle condition is where the device

monitors the SDA and SCK lines waiting for the start condition

and correct transmitted address. The R/W bit determines the

direction of the data. Logic 0 on the LSB of the first byte means

that the master writes information to the peripheral. Logic 1 on

the LSB of the first byte means that the master reads information

from the peripheral.

The ADN2855 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long supporting the 7-bit addresses

plus the R/W bit. The ADN2855 has six subaddresses to enable

the user-accessible internal registers (see Table 7 through Table

11). It, therefore, interprets the first byte as the device address

and the second byte as the starting subaddress. Autoincrement

mode is supported, allowing data to be read from or written to the

starting subaddress and each subsequent address without

manually addressing the subsequent subaddress. A data transfer

is always terminated by a stop condition. The user can also

access any unique subaddress register on a one-by-one basis

without updating all registers.

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCK high period, the

user should issue one start condition, one stop condition, or a

single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADN2855 does not

issue an acknowledge, and returns to the idle condition. If the

Data Sheet ADN2855

Rev. B | Page 13 of 20

user exceeds the highest subaddress while reading back in

autoincrement mode, then the highest subaddress register

contents continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. In a no-

acknowledge condition, the SDATA line is not pulled low on the

ninth pulse. See Figure 11 and Figure 12 for sample write and

read data transfers and Figure 13 for a more detailed timing

diagram.

REFERENCE CLOCK

A reference clock is required to perform burst mode clock and

data recovery with the ADN2855. The reference clock must be

frequency locked to the incoming burst data. It is assumed that

the incoming burst data from the ONT is timed by a clock recov-

ered from the downstream data from the OLT and, therefore,

is inherently frequency clocked to the OLT system clock. The

reference clock can be driven differentially or single-ended. See

Figure 15 and Figure 16 for sample configurations.

The REFCLK input buffer accepts any differential signal with

a peak-to-peak differential amplitude of greater than 100 mV

(for example, LVPECL or LVDS) or a standard single-ended

low voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not critical.

06660-013

REFCLKP

REFCLKN

100kΩ 100kΩ

BUFFER

VCC/2

Figure 15. Differential REFCLK Configuration

06660-014

REFCLKP

REFCLKN

100kΩ 100kΩ

BUFFER

VCC/2

OUT

VCC

OSC

CLK

Figure 16. Single-Ended REFCLK Configuration

The ADN2855 must be operated in lock to reference clock

mode when in burst data recovery mode. Lock to reference

clock mode is enabled by writing a 1 to I

C Control Register

CTRLA, Bit 0. A frequency acquisition in this mode must be

initiated by writing a 1 to 0 transition to CTRLB[5].

Using the Reference Clock to Lock onto Data

In this mode, the ADN2855 locks onto a frequency derived

from the reference clock according to the following equation:

Data Rate/2

CTRLA[5:2]

= REFCLK/2

CTRLA[7:6]

The user must know exactly what the data rate is and provide

a reference clock that is a function of this rate. The reference

clock can be anywhere between 10 MHz and 200 MHz. By

default, the ADN2855 expects a reference clock of between

10 MHz and 25 MHz. If it is between 25 MHz and 50 MHz,

50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user

needs to configure the ADN2855 to use the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7:6].

Table 12. CTRLA Settings

Bit No. Description

CTRLA[7:6] F

REF

range

00 = 10 MHz to 25 MHz

01 = 25 MHz to 50 MHz

10 = 50 MHz to 100 MHz

11 = 100 MHz to 200 MHz

CTRLA[5:2] Data rate/DIV_F

REF

ratio

0000 = 1

0001 = 2

…

n = 2

…

1000 = 256

The user can specify a fixed integer multiple of the reference clock

to lock onto using CTRLA[5:2], where CTRLA should be set to

the data rate/DIV_F

REF

ratio, where DIV_F

REF

represents the

divided-down reference referred to the 10 MHz to 25 MHz band.

For example, if the reference clock frequency is 38.88 MHz and

the input data rate is 622.08 Mbps, then CTRLA[7:6] should be

set to 01 to give a divided-down reference clock of 19.44 MHz.

CTRLA[5:2] should be set to 0101, that is, 5, because

622.08 Mbps/19.44 MHz = 2

While the ADN2855 is operating in lock to reference clock mode,

if the user ever changes the reference frequency, the F

REF

range

(CTRLA[7:6]), or the data rate/DIV_F

REF

ratio (CTRLA[5:2]),

this must be followed by writing a 0 to 1 transition into the

CTRLB[5] bit to initiate a new frequency acquisition.

ADN2855 Data Sheet

Rev. B | Page 14 of 20

OUTPUT MODES

Parallel or Serial Output Mode

The output of the ADN2855 can be configured in a 4-bit

parallel output nibble mode, or it can be configured in a

serial output mode. The default mode of operation is for

the Rx data to be deserialized and output in a 4-bit nibble,

present at DATxP/DATxN, where the earliest bit is present

on DAT3P/DAT3N. Setting Bit CTRLC[5] = 1 reverses the

order of the DATxP/DATxN bus such that the earliest bit is

present on DAT0P/DAT0N.

Setting bit CTRLD[7] = 1 puts the device into serial output

mode. In this mode, the Rx data is present on DAT0P/DAT0N.

Double Data Rate Mode

The default output mode for the ADN2855 is for a 4-bit deseria-

lized output with a full rate output clock, where the output

data switches on the rising edge of the output clock. When

the ADN2855 is programmed to be in parallel output mode

(CTRLD[7] = 0), setting CTRLC[4] = 1 puts the ADN2855

clock output through divide-by-two circuitry, allowing direct

interfacing to FPGAs that support data clocking on both rising

and falling edges.

When the ADN2855 is in serial output mode (deserializer off),

CTRLD[7] = 1, the default is for a half rate output clock where

the data switches on both falling and rising edges of the output

clock. Setting CTRLD[0] = 1 sets the serial clock output into full

rate mode so that the output data switches only on the rising edges

of the output clock.

RxCLK Phase Adjust

The ADN2855 provides the option of adjusting the phase of the

output clock with respect to the parallel output data. In parallel

mode, the duration of each bit is 4 UI wide, due to the deserializa-

tion. There are three additional phase adjust options other than

the baseline (that is, CLK edge in the center of the data eye): +2 UI,

+0.5 UI, and −1.5 UI. The output clock phase adjustment feature

is accessed via CTRLC[3:2]. See Table

for details.

DISABLE OUTPUT BUFFERS

The ADN2855 provides the option of disabling the output buffers

for power savings. The clock output buffers can be disabled by

setting CTRLD[5] = 1. For additional power savings (for example,

in a low power standby mode), the data output buffers can also

be disabled by setting CTRLD[6] = 1.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

ADN2855ACPZ-R7

Mfr. #:

Buy ADN2855ACPZ-R7

Manufacturer:

Analog Devices Inc.

Description:

Timers & Support Products BDR

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADN2855ACPZ-R7

ADN2855ACPZ-R7

Products related to this Datasheet