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ADN2855ACPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADN2855 Data Sheet
Rev. B | Page 6 of 20
RESET TIMING OPTIONS
06660-007
OPTION 1
END OF
PACKET
OPTION 2
END OF
P
ACKET
OPTION 3
END OF
PACKET
RESET PULSE
0 BYTES TO 8 BYTES
0 BYTES TO 8 BYTES
RESET PULSE
(2 BYTES)
200µs BETWEEN BURSTS
200µs BETWEEN BURSTS
RESET PULSE
(2 BYTES)
GUARD TIME (4 BYTES)
THIS ASSUMES NO NOISE IS PRESENT
ON THE INPUTS TO THE ADN2855
THIS ASSUMES NO NOISE IS PRESENT AT THE INPUTS
TO THE ADN2855 BETWEEN BURSTS.
IF THIS IS THE CASE, THE RESET PULSE MUST BEASSERTED UNTIL THE TIME THA
T THE
INPUT DATA
TO THE ADN2855 BECOMES VALID, IDEALLY JUST PRIOR TO THE START OF THE
PREAMBLE. THERE IS NO REQUIREMENT THAT FOLLOWING THE DEASSERTION OF THE
RESET SIGNAL THE
ADN2855 MUST SEE AT LEAST 13 BITS OF THE PREAMBLE.
Figure 8. Reset Timing Options
Data Sheet ADN2855
Rev. B | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V,
C
F
= 0.47 μF, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE − 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified for 4-layer board with exposed paddle soldered
to VEE.
Table 5. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
32-Lead LFCSP (CP-32-20) 35.1 2.4 °C/W
ESD CAUTION
ADN2855 Data Sheet
Rev. B | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06660-002
SCK
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
VCC
VEE
SQUELCH
CLKOUTN
CLKOUTP
VCC
DAT0P
DAT0N
SADDR[2]
RESET
SADDR[1]
NIN
PIN
VCC
VEE
SDA
VCC
VEE
DAT1P
DAT1N
NOTES
1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE THAT MUST BE CONNECTED TO VEE (GND).
DAT2P
DAT2N
DAT3P
DAT3N
PIN 1
INDICATOR
DATAV
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
ADN2855
TOP VIEW
(Not to Scale)
Figure 9. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 SADDR[2] DI Slave Address Bit 2.
2 RESET DI RESET Pulse to be Asserted Prior to Incoming Burst. Active high.
3 SADDR[1] DI Slave Address Bit 1.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 VCC P 3.3 V Power.
7 VEE P GND.
8 SDA IO I
2
C Data I/O.
9 SCK DI I
2
C Clock.
10 REFCLKP DI Differential REFCLK Input.
11 REFCLKN DI Differential REFCLK Input.
12 VCC P 3.3 V Power.
13 VEE P GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16
DATAV
DO Output Data Valid. LVTTL active low.
17 DAT3N DO Differential Deserialized Output MSB, LVDS.
18 DAT3P DO Differential Deserialized Output MSB, LVDS.
19 DAT2N DO Differential Deserialized Output Bit 2, LVDS.
20 DAT2P DO Differential Deserialized Output Bit 2, LVDS.
21 DAT1N DO Differential Deserialized Output Bit 1, LVDS.
22 DAT1P DO Differential Deserialized Output Bit 1, LVDS.
23 VEE P GND.
24 VCC P 3.3 V Power.
25 DAT0N DO Differential Deserialized Output LSB, LVDS
26 DAT0P DO Differential Deserialized Output LSB, LVDS
27 VCC P 3.3 V Power
28 CLKOUTP DO Differential Recovered Clock Output, LVDS.
29 CLKOUTN DO Differential Recovered Clock Output, LVDS.
30 SQUELCH DI Squelch Data and/or Clock Outputs. Active high.
31 VEE P GND
32 VCC P 3.3 V Power.
33 (EPAD) Exposed Pad (EPAD) P There is an exposed pad on the bottom of the package that must be connected to VEE (GND).
1
P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, IO = digital input/output.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADN2855ACPZ-R7

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Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products BDR
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