13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
NO OPERATION
RCLK
REN
EF
tCLK
tCLKH tCLKL
tENS tENH
tREF tREF
VALID DATA
tA
tOLZ
tOE
tOHZ
Q0 - Q17
OE
WCLK
WEN
t
SKEW1
(1)
3139 drw 07
WCLK
D
0
- D
17
WEN
RCLK
EF
Q
0
- Q
17
REN
t
DS
t
SKEW1
t
ENS
t
REF
t
A
0
12 3
D
DDD
01
DD
(first valid write)
t
OE
t
OLZ
OE
t
A
t
FRL
(1)
D
4
t
ENS
3139 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing
applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
