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72805LB15PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
22
Figure 27.
OROR
OROR
OR
Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered
EFEF
EFEF
EF
(IDT Standard Timing)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the rising
edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
NO OPERATION
RCLK
REN
EF
t
CLKL
t
ENH
t
REF
LAST WORD
t
A
t
OLZ
t
OE
Q
0
- Q
17
OE
WCLK
WEN
3139 drw 26
D
0
- D
17
t
ENS
t
ENS
t
ENH
t
DS
t
DH
FIRST WORD
t
OHZ
t
CLK
12
t
REF
t
SKEW1
t
CLKH
(1)
W
1
W
2
W
4
W
[n +2]
W
[n+3]
WCLK
WEN
D
0 - D17
RCLK
t
DH
t
DS
t
ENS
t
SKEW1
REN
Q0
-
Q17
t
DS
t
A
t
REF
OR
W
1
DATA IN OUTPUT REGISTER
(1)
W
3
1
2
3
t
ENH
t
REF
3139 drw 27
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72805LB/72815LB/
72825LB/72845LB may be used as a stand-alone device when the application
requirements are for 256/512/1,024/4,096 words or less. These FIFOs are in
a single Device Configuration when the First Load (FL), Write Expansion In
(WXI) and Read Expansion In (RXI) control inputs are configured as (FL, RXI,
WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure
28).
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 Synchronous FIFO
(One of the two FIFOs contained in the IDT72805LB/72815LB/72825LB/72845LB)
Figure 29. Block Diagram of the two FIFOs contained in one IDT72805LB/72815LB/72825LB/72845LB
configured for a 36-bit Width Expansion
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using one
IDT72805LB/72815LB/72825LB/72845LBs. Any word width can be attained
by adding additional IDT72805LB/72815LB/72825LB/72845LBs. These FIFOs
are in a single Device Configuration when the First Load (FL), Write Expansion
In (WXI) and Read Expansion In (RXI) control inputs are configured as (FL,
RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset
(Figure 29). Please see the Application Note AN-83.
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
DATA IN (D
0
- D
17
)
DATA OUT (Q
0
- Q
17
)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
RESET (RS)
IDT
72805
72815
72825
72845
3139 drw 28
FL RXI WXI
FIFO A OR B
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG/INPUT
READY (FF/IR)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
EMPTY FLAG/OUTPUT
READY (EF/OR)
PROGRAMMABLE (PAF)
RESET (RS)
FIFO A
FIFO B
RESET (RS)
36
36
18 18
18
18
FF/IR E F/OR
3139 drw 29
FL WXI RXI
FL WXI RXI
FF/IR E F/OR
NOTE:
1. Do not connect any output control signals directly together.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
24
Figure 30. Block Diagram of 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/4,096 words of buffering. Figure 30 shows Depth Expansion
using one IDT72805LB/72815LB/72825LB/72845LBs. Maximum depth is
limited only by signal loading. Follow these steps:
1.The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the
Write Expansion In (WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read
Expansion In (RXI) pin of the next device. See Figure 30.
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN DATA OUT
RESET
FIRST LOAD (FL)
Vcc
WXOA
WXIA
RXOA
RXIA
WXOB
WXIB
RXOB
RXIB
IDT72845
FFA/IRA
PAFA
EFA/ORA
PAEA
PAFB
PAEB
EF/OR
PAE
FF/IR
PAF
3139 drw 30
RCLKB
RENB
OEB
WCLKB
WENB
RSB
FLA
RCLKA
RENA
OEA
WCLKA
WENA
RSA
LDA
DAn
QAn
DBn
QBn
LDB
FIFO A
4,096 x 18
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

72805LB15PF

Mfr. #:
Buy 72805LB15PF
Manufacturer:
IDT
Description:
FIFO 256 X 18 SYNCHRONOUS FIFO
Lifecycle:
New from this manufacturer.
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