25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
3139 drw 31
n
n n
RXI
HF
72805
72815
72825
72845
WXI
FL
V
CC
GND
(0,1)
72805
72815
72825
72845
RXI
WXI
FL
V
CC
GND
(0,1)
PAF
HF
PAE
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72805LB/72815LB/72825LB/72845LB
devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the OR flag.
The “ripple down” delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
26
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
BLANK
I
(1)
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Process /
Temperature
Range
3139 drw32
Commercial Only
Com'l & Ind'l
Commercial Only
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BG
(3)
PF
Ball Grid Array (PBGA, BG121)
Thin Quad Flatpack (TQFP, PK128)
10
15
25
LB
Low Power
72805
72815
72825
72845
256 x18 Dual SyncFIFO
512 x18 Dual SyncFIFO
1,024 x18 Dual SyncFIFO
4,096 x18 Dual SyncFIFO
X
Green
G
(2)
BLANK
8
Tray
Tape and Reel
X
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Green parts are available. For specific speeds and packages contact your sales office.
3. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade.
DATASHEET DOCUMENT HISTORY
05/01/2001 pgs. 1, 5, 6, and 26.
02/12/2003 pgs. 1, 2, and 26.
11/30/2004 pg. 5.
02/22/2006 pgs. 1 and 26.
01/13/2009 pg. 26.
05/23/2016 pgs. 1-26.

72805LB15PF

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 256 X 18 SYNCHRONOUS FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union