COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
16
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825 and 4,096 for the IDT72845.
In FWFT Mode:
D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825 and 4,097 for the IDT72845.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825 and 4,096 for the IDT72845.
In FWFT Mode:
D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825 and 4,097 for the IDT72845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1) words in FIFO
RCLK
t
PAFA
REN
(1)
3139 drw 14
D - m words in FIFO
D - (m + 1) words in FIFO
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
3139 drw 15
t
CLKL
t
CLKH
D/2 words in FIFO
(2)
,
[
+ 1
]
words in FIFO
(3)
D/2 + 1 words in FIFO
(2)
,
[
+ 2
]
words in FIFO
(3)
D-1
2
D/2 words in FIFO
(2)
,
[
+ 1
]
words in FIFO
(3)
D-1
2
D-1
2
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
Figure 18. Write Expansion In Timing
Figure 19. Read Expansion In Timing
WCLK
WEN
t
ENS
WXO
t
CLKH
t
XO
Note 1
t
XO
3139 drw 16
RCLK
REN
t
ENS
RXO
t
CLKH
t
XO
Note 1
t
XO
3139 drw 17
WXI
WCLK
t
XI
t
XIS
3139 drw 18
RXI
RCLK
t
XI
t
XIS
3139 drw 19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
18
Figure 20. Write Timing with Synchronous Programmable Flags (FWFT Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, then the
OR deassertion may be delayed one extra RCLK cycle.
2. t
SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 257 words for the IDT72805, 513 words for the IDT72815, 1,025 words for the IDT72825 and 4,097 words for the IDT72845.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,1) during Reset.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
- D
17
RCLK
t
DH
t
DS
t
ENS
t
SKEW1
REN
Q
0
- Q
17
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
3139 drw 20
DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
1
D-1
][
W
D-1
][
W
D-1
][
W

72805LB15PF

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 256 X 18 SYNCHRONOUS FIFO
Lifecycle:
New from this manufacturer.
Delivery:
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