CS5530-CSZ Datasheet CS5530-CSZ | P1-P3

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CS5530

24-bit ADC with Ultra-low-noise Amplifier

Features & Description

 Chopper-stabilized Instrumentation

Amplifier, 64X

• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)

• 500 pA Input Current



Digital Gain Scaling up to 40x

 Delta-sigma Analog-to-digital Converter

• Linearity Error: 0.0015% FS

• Noise Free Resolution: Up to 19 bits



Scalable V

REF

Input: Up to Analog Supply

 Simple Three-wire Serial Interface

• SPI™ and Microwire™ Compatible

• Schmitt-trigger on Serial Clock (SCLK)



Onboard Offset and Gain Calibration

Registers

 Selectable Word Rates: 6.25 to 3,840 Sps

 Selectable 50 or 60 Hz Rejection

 Power Supply Configurations

• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V

• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V

• VA+ = +3 V; VA- = -3 V; VD+ = +3 V

General Description

The CS5530 is a highly integrated ∆Σ Analog-to-Digital

Converter (ADC) which uses charge-balance techniques

to achieve 24-bit performance. The ADC is optimized for

measuring low-level unipolar or bipolar signals in weigh

scale, process control, scientific, and medical

applications.

To accommodate these applications, the ADC

includes

a very-low-noise, chopper-stabilized instrumentation

amplifier (12 nV/√Hz

@ 0.1 Hz) with a gain of 64X. This

device also includes a fourth-order ∆Σ modulator fol-

lowed by a digital filter

which provides twenty selectable

output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,

120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and

3840 Sps (MCLK = 4.9152 MHz).

To ease communication between the ADC and a micro-

controller, the converter includes a simple three-wire se-

rial interface which is SPI and Microwire compatible with

a Schmitt-trigger input on the serial clock (SCLK).

High dynamic range, programmable output rates, and

flexible power supply options make this device an ideal

solution for weigh scale and process control

applications.

ORDERING INFORMATION

See page 35.

VA+ C1 C2 VREF+ VREF- VD+

DIFFERENTIAL

ORDER

∆Σ

MODULATOR

PROGRAMMABLE

SINC FIR FILTER

AIN1+

AIN1-

SERIAL

INTERFACE

LATCH

CLOCK

GENERATOR

CALIBRATION

SRAM/CONTROL

LOGIC

DGND

SDI

SDO

SCLK

OSC2OSC1A1A0VA-

64X

NOV ‘06

DS742A4

CS5530

2 DS742A4

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4

ANALOG CHARACTERISTICS................................................................................ 4

TYPICAL NOISE-FREE RESOLUTION (BITS)........................................................ 6

5 V DIGITAL CHARACTERISTICS .......................................................................... 7

3 V DIGITAL CHARACTERISTICS .......................................................................... 7

DYNAMIC CHARACTERISTICS .............................................................................. 8

ABSOLUTE MAXIMUM RATINGS ........................................................................... 8

SWITCHING CHARACTERISTICS .......................................................................... 9

2. GENERAL DESCRIPTION .............................................................................................. 11

2.1. Analog Input ........................................................................................................... 11

2.1.1. Analog Input Span .......................................................................................... 12

2.1.2. Voltage Noise Density Performance ........................................................... 12

2.1.3. No Offset DAC ............................................................................................ 12

2.2. Overview of ADC Register Structure and Operating Modes .................................. 12

2.2.1. System Initialization .................................................................................... 12

2.2.2. Command Register Descriptions ................................................................ 14

2.2.3. Serial Port Interface .................................................................................... 16

2.2.4. Reading/Writing On-Chip Registers ............................................................ 17

2.3. Configuration Register ........................................................................................... 17

2.3.1. Power Consumption ................................................................................... 17

2.3.2. System Reset Sequence ............................................................................ 17

2.3.3. Input Short .................................................................................................. 17

2.3.4. Voltage Reference Select .......................................................................... 17

2.3.5. Output Latch Pins ....................................................................................... 18

2.3.6. Filter Rate Select ........................................................................................ 18

2.3.7. Word Rate Select ........................................................................................ 18

2.3.8. Unipolar/Bipolar Select ............................................................................... 18

2.3.9. Open Circuit Detect .................................................................................... 18

2.3.10. Configuration Register Description ........................................................... 19

2.4. Calibration .............................................................................................................. 21

2.4.1. Calibration Registers .................................................................................. 21

2.4.2. Gain Register ............................................................................................. 21

2.4.3. Offset Register ........................................................................................... 21

2.4.4. Performing Calibrations .............................................................................. 22

2.4.5. System Calibration ...................................................................................... 22

2.4.6. Calibration Tips ........................................................................................... 22

2.4.7. Limitations in Calibration Range ................................................................. 23

2.5. Performing Conversions ........................................................................................ 23

2.5.1. Single Conversion Mode ............................................................................. 23

2.5.2. Continuous Conversion Mode .................................................................... 24

2.6. Using Multiple ADCs Synchronously ..................................................................... 25

2.7. Conversion Output Coding .................................................................................... 25

2.7.1. Conversion Data Output Descriptions ........................................................ 26

2.8. Digital Filter ............................................................................................................ 27

2.9. Clock Generator ..................................................................................................... 28

2.10. Power Supply Arrangements ................................................................................. 28

2.11. Getting Started ....................................................................................................... 31

2.12. PCB Layout ............................................................................................................ 31

3. PIN DESCRIPTIONS ...................................................................................................... 32

Clock Generator ......................................................................................................32

Control Pins and Serial Data I/O .............................................................................32

Measurement and Reference Inputs ......................................................................33

Power Supply Connections .....................................................................................33

4. SPECIFICATION DEFINITIONS ..................................................................................... 33

5. PACKAGE DRAWINGS .................................................................................................. 34

6. ORDERING INFORMATION .......................................................................................... 35

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................... 35

CS5530

DS742A4 3

LIST OF FIGURES

Figure 1. SDI Write Timing (Not to Scale)...............................................................................10

Figure 2. SDO Read Timing (Not to Scale).............................................................................10

Figure 3. Front End Configuration...........................................................................................11

Figure 4. Input Model for AIN+ and AIN- Pins.........................................................................11

Figure 5. Measured Voltage Noise Density.............................................................................12

Figure 6. CS5530 Register Diagram.......................................................................................13

Figure 7. Command and Data Word Timing ...........................................................................16

Figure 8. Input Reference Model when VRS = 1 ....................................................................18

Figure 9. Input Reference Model when VRS = 0 ....................................................................18

Figure 10. System Calibration of Offset ..................................................................................22

Figure 11. System Calibration of Gain ....................................................................................22

Figure 12. Synchronizing Multiple ADCs.................................................................................25

Figure 13. Digital Filter Response (Word Rate = 60 Sps).......................................................27

Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz ...............................................................27

Figure 15. 120 Sps Filter Phase Plot to 120 Hz......................................................................27

Figure 16. Z-Transforms of Digital Filters................................................................................27

Figure 17. On-chip Oscillator Model........................................................................................28

Figure 18. CS5530 Configured with a Single +5 V Supply .....................................................29

Figure 19. CS5530 Configured with ±2.5 V Analog Supplies..................................................29

Figure 20. CS5530 Configured with ±3 V Analog Supplies.....................................................30

LIST OF TABLES

Table 1. Conversion Timing for Single Mode..........................................................................24

Table 2. Conversion Timing for Continuous Mode..................................................................24

Table 3. Output Coding...........................................................................................................25

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

CS5530-CSZ

Mfr. #:

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Manufacturer:

Cirrus Logic

Description:

IC ADC 24BIT SIGMA-DELTA 20SSOP

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CS5530-CSZ