CS5530
DS742A4 19
2.3.10 Configuration Register Description
PSS (Power Save Select)[31]
0 Standby Mode (Oscillator active, allows quick power-up).
1 Sleep Mode (Oscillator inactive).
PDW (Power Down Mode)[30]
0 Normal Mode
1 Activate the power save select mode.
RS (Reset System)[29]
0 Normal Operation.
1 Activate a Reset cycle. See System Reset Sequence in the datasheet text.
RV (Reset Valid)[28]
0 Normal Operation
1 System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read.
IS (Input Short)[27]
0 Normal Input
1 All signal input pairs for each channel are disconnected from the pins and shorted internally.
NU (Not Used)[26]
0 Must always be logic 0. Reserved for future upgrades.
VRS (Voltage Reference Select)[25]
0 2.5 V < V
REF
[(VA+) - (VA-)]
11 V V
REF
2.5V
A1-A0 (Output Latch bits)[24:23]
The latch bits (A1 and A0) will be set to the logic state of these bits when the Configuration register is written.
Note that these logic outputs are powered from VA+ and VA-.
00 A1 = 0, A0 = 0
01 A1 = 0, A0 = 1
10 A1 = 1, A0 = 0
11 A1 = 1, A0 = 1
NU (Not Used)[22:20]
0 Must always be logic 0. Reserved for future upgrades.
Filter Rate Select, FRS[19]
0 Use the default output word rates.
1 Scale all output word rates and their corresponding filter characteristics by a factor of 5/6.
NU (Not Used)[18:15]
0 Must always be logic 0. Reserved for future upgrades.
D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
PSS PDW RS RV IS NU VRS A1 A0 NU NU NU FRS NU NU NU
D15 D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
NU WR3 WR2 WR1 WR0 UP/BP
OCDNUNUNUNUNUNUNUNUNU
CS5530
20 DS742A4
WR3-WR0 (Word Rate) [14:11]
The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will
scale linearly with the clock frequency used. The very first conversion using continuous conversion mode
will last longer, as will conversions done with the single conversion mode. See the section on Performing
Conversions and Tables 1 and 2 for more details.
Bit WR (FRS = 0) WR (FRS = 1)
0000 120 Sps 100 Sps
0001 60 Sps 50 Sps
0010 30 Sps 25 Sps
0011 15 Sps 12.5 Sps
0100 7.5 Sps 6.25 Sps
1000 3840 Sps 3200 Sps
1001 1920 Sps 1600 Sps
1010 960 Sps 800 Sps
1011 480 Sps 400 Sps
1100 240 Sps 200 Sps
All other combinations are not used.
U/B (Unipolar / Bipolar) [10]
0 Select Bipolar mode.
1 Select Unipolar mode.
OCD (Open Circuit Detect Bit) [9]
When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel
select bits. Note that the 300nA current source is rated at 25°C. This feature is particularly useful in ther-
mocouple applications when the user wants to drive a suspected open thermocouple lead to a supply rail.
0 Normal mode.
1 Activate current source.
NU (Not Used) [8:0]
0 Must always be logic 0. Reserved for future upgrades.
CS5530
DS742A4 21
2.4 Calibration
Calibration is used to set the zero and gain slope of
the ADC’s transfer function. The CS5530 provides
system calibration.
Note: After the ADC is reset, it is functional and can
perform measurements without being
calibrated (remember that the VRS bit in the
configuration register must be properly
configured). If the converter is operated
without calibraton, the converter will utilize
the initialized values of the on-chip registers
(Offset = 0.0; Gain = 1.0) to calculate output
words. Any initial offset and gain errors in the
internal circuitry of the chip will remain.
2.4.1 Calibration Registers
The CS5530 converter has an offset register that is
used to set the zero point of the converter’s transfer
function. As shown in Offset Register section, one
LSB in the offset register is 1.835007966 X 2
-24
proportion of the input span (bipolar span is 2 times
the unipolar span, gain register = 1.000...000 deci-
mal). The MSB in the offset register determines if
the offset to be trimmed is positive or negative (0
positive, 1 negative). Note that the magnitude of
the offset that is trimmed from the input is mapped
through the gain register. The converter can typi-
cally trim ±100 percent of the input span. As shown
in the Gain Register section, the gain register spans
from 0 to (64 - 2
-24
). The decimal equivalent mean-
ing of the gain register is
where the binary numbers have a value of either
zero or one (b
D29
is the binary value of bit D29).
While gain register settings of up to 64 - 2
-24
are
available, the gain register should never be set to
values above 40.
2.4.2 Gain Register
The gain register span is from 0 to (64-2
-24
). After Reset D24 is 1, all other bits are ‘0’.
2.4.3 Offset Register
One LSB represents 1.835007966 X 2
-24
proportion of the input span (bipolar span is 2 times unipolar span).
Offset and data word bits align by MSB. After reset, all bits are ‘0’.
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.
Db
D29
2
5
b
D28
2
4
b
D27
2
3
b
D0
2
24
)++++ b
Di
2
24 i+()
i 0=
29
==
Decimal Point
MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
NU NU
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
0000000100000000
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
22
2
-23
2
-24
0000000000000000
MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Sign
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
0000000000000000
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
NU NU NU NU NU NU NU NU
0000000000000000

CS5530-CSZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
IC ADC 24BIT SIGMA-DELTA 20SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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