16
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
synchronizing clock begins the first synchronization cycle if it occurs at time
t
SKEW2 or greater after the read that reduces the number of words in memory
to [4,096-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may
be the first synchronization cycle (see Figure 25 and 26).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between Port A and Port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port data transfer operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes data to the Mail 1 Register when
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selected Port B bus size is also 36 bits, then the usable width of the Mail1 register
employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail1 Register employs data lines A0-A17. (In this case,
A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then
the usable width of the Mail1 Register employs data lines A0-A8. (In this case,
A9-A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is also 36 bits, then the usable width of
the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines B0-B17. (In this
case, B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits,
then the usable width of the Mail2 Register employs data lines B0-B8. (In this
case, B9-B35 are don’t care inputs.)
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port Mailbox select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian select feature has no effect
on mailbox data. For mail register and Mail Register Flag timing diagrams, see
Figure 27 and 28.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bit byte format for data read from FIFO1 or written to FIFO2. The levels
applied to the Port B Bus Size select (SIZE) and the Bus-Match select (BM)
determine the Port B bus size. These levels should be static throughout FIFO
operation. Both bus size selections are implemented at the completion of
Master Reset, by the time the Full/Input Ready flag is set HIGH, as shown in
Figure 2.
Two different methods for sequencing data transfer are available for Port
B when the bus size selection is either byte- or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
byte first). The level applied to the Big-Endian select (BE) input during the LOW-
to-HIGH transition of MRS1 and MRS2 selects the endian method that will be
active during FIFO operation. BE is a don’t care input when the bus size
selected for Port B is long word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready flag is set HIGH,
as shown in Figure 2.
Only 36-bit long word data is written to or read from the two FIFO memories
on the IDT72V3664. Bus-matching operations are done after data is read from
the FIFO1 RAM and before data is written to the FIFO2 RAM. These bus-
matching operations are not available when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus selections limit the
width of the data bus that can be used for mail register operations. In this case,
only those byte lanes belonging to the selected word- or byte-size bus can
carry mailbox data. The remaining data outputs will be indeterminate. The
remaining data inputs will be don’t care inputs. For example, when a word-
size bus is selected, then mailbox data can be transmitted only between A0-
A17 and B0-B17. When a byte-size bus is selected, then mailbox data can be
transmitted only between A0-A8 and B0-B8. (See Figures 27 and 28).
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the
FIFO1 output register. If byte or word size is implemented on Port B, only the
first one or two bytes appear on the selected portion of the FIFO1 output register,
with the rest of the long word stored in auxiliary registers. In this case,
subsequent FIFO1 reads output the rest of the long word to the FIFO1 output
register in the order shown by Figure 2.
When reading data from FIFO1 in byte or word format, the unused B0-B35
outputs are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data written
to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary
registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 2.
When writing data to FIFO2 in byte or word format, the unused B0-B35 inputs
are don't care inputs.
