22
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
SIZE MODE
(1)
DATA WRITTEN TO FIFO1 READ DATA READ FROM FIFO1
NO.
BM SIZE BE A35-A27 A26-A18 A17-A9 A8-A0 B17-B9 B8-B0
HLH A B C D1 A B
2C D
HLL A B C D1 C D
2A B
DATA SIZE TABLE FOR WORD READS FROM FIFO1
Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
SIZE MODE
(1)
DATA WRITTEN TO FIFO1 DATA READ FROM FIFO1
BM SIZE BE A35-A27 A26-A18 A17-A9 A8-A0 B35-B27 B26-B18 B17-B9 B8-B0
LXXA B CDABCD
NOTE:
1. Read From FIFO1.
DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1
Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
NOTE:
1. Unused word B18-B35 are indeterminate for word-size reads.
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
4664 drw 13
CLKB
EFB/ORB
ENB
MBB
CSB
W/RB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
A
t
MDV
t
EN
t
A
t
ENS2
t
ENH
t
ENS2
t
ENH
W1
W2 W3
(1)
(1)
t
ENH
t
DIS
No Operation
B0-B35
(FWFT Mode)
t
EN
W2
t
DIS
W1
Previous Data
B0-B35
(Standard Mode)
t
MDV
t
A
OR
t
A
HIGH
(1)(1)
(1)
CLKB
ENB
EFB/ORB
W/RB
CSB
HIGH
4664 drw 14
B0-B17
(Standard Mode)
B0-B17
(FWFT Mode)
OR
Previous Data
t
DIS
t
A
t
A
t
ENS2
t
ENH
No Operation
Read 1
t
A
t
A
Read 1
Read 2
Read 2
Read 3
t
DIS
MBB
t
EN
t
MDV
t
EN
t
MDV
23
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE
(1)
DATA WRITTEN TO FIFO1 READ DATA READ FROM FIFO1
NO.
BM SIZE BE A35-A27 A26-A18 A17-A9 A8-A0 B8-B0
HH H A B C D
HH L A B C D
1 A
2 B
3 C
4 D
1 D
2 C
3 B
4 A
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.
NOTE:
1. Read From FIFO2.
EFB/ORB
MBB
CSB
W/RB
ENB
CLKB
HIGH
B0-B8
B0-B8
Read 5Read 2 Read 3
Read 4Read 3
Read 4
Previous Data
Read 2
No Operation
t
DIS
t
DIS
t
A
t
A
t
A
t
A
t
A
t
A
t
ENS2
t
ENH
t
A
t
A
Read 1
(Standard Mode)
(FWFT Mode)
t
EN
t
MDV
t
MDV
t
EN
OR
Read 1
4664 drw 15
4664 drw16
CLKA
EFA/ORA
ENA
MBA
CSA
W/RA
tCLK
tCLKH
tCLKL
tENS2
tA
tMDV
tEN
t
A
tENS2
tENH
tENS2
tENH
W1
W2
W3
(1)
(1)
tENH
tDIS
No Operation
A0-A35
(FWFT Mode)
tEN
W2
(1)
(1)
tDIS
W1Previous Data
A0-A35
(Standard Mode)
tMDV
tA
OR
tA
HIGH
(1)
24
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CSA
WRA
MBA
IRA
A0-A35
CLKB
ORB
CSB
W/RB
MBB
ENA
ENB
B0-B35
CLKA
4664 drw17
12
3
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDS
tDH
tSKEW1
tCLK
tCLKL
tREF tREF
tENS2 tENH
tA
Old Data in FIFO1 Output Register
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
tCLKH
W1
HIGH
(1)

72V3664L10PF

Mfr. #:
Manufacturer:
Description:
FIFO BIDIRECTIONAL/ BUS 4KX36X2
Lifecycle:
New from this manufacturer.
Delivery:
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