1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 16.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
CSA
WRA
MBA
FFA
A0-A35
CLKB
EFB
CSB
W/RB
MBB
ENA
ENB
B0-B35
CLKA
12
4664 drw18
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDStDH
tSKEW1
tCLK
tCLKL
tENS2
tENH
tA
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
tCLKH
W1
HIGH
(1)
tREF
tREF
26
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
NOTES:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKB edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2.If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
CSB
W/RB
MBB
IRB
B0-B35
CLKA
ORA
CSA
W/RA
MBA
ENB
ENA
A0-A35
CLKB
4664 drw19
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
(1)
t
CLK
t
CLKH
t
REF
t
REF
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output RegisterW1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
27
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
NOTES:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2.If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 18.
EFAEFA
EFAEFA
EFA
Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
