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72V3664L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
34
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
CLKA
ENB
CLKB
RT1
4664 drw31
t
RSTS
t
RSTH
t
REF
(2)
B0-Bn
RTM
EFB
t
REF
(2)
W1
Wx
t
A
13
4
2
1
342
t
RTMS
t
RTMH
t
ENS2
t
ENH
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit
setup procedure. D = 4,096 for the IDT72V3664.
Figure 29. Retransmit Timing for FIFO1 (IDT Standard Mode)
CLKB
ENA
CLKA
RT2
4664 drw32
tRSTS
tRSTH
tREF
(2)
A0-An
RTM
EFA
tREF
(2)
W1
Wx
tA
13
4
2
1
342
t
RTMS
tRTMH
tENS2
tENH
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFB will be LOW throughout the Retransmit
setup procedure. D = 4,096 for the IDT72V3664.
Figure 30. Retransmit Timing for FIFO2 (IDT Standard Mode)
35
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
CLKA
ENB
CLKB
RT1
4664 drw33
t
RSTS
t
RSTH
t
REF
(2)
B0-Bn
RTM
ORB
t
REF
(2)
W1
Wx
13
4
2
1
342
t
RTMS
t
RTMH
LOW
t
A
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 4,097 for the IDT72V3664.
Figure 31. Retransmit Timing for FIFO1 (FWFT Mode)
CLKB
ENA
CLKA
RT2
4664 drw34
tRSTS tRSTH
tREF
(2)
A0-An
RTM
ORA
tREF
(2)
W1
Wx
tA
13
4
2
1
342
t
RTMS
tRTMH
LOW
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit
setup procedure. D = 4,097 for the IDT72V3664.
Figure 32. Retransmit Timing for FIFO2 (FWFT Mode)
36
COMMERCIAL TEMPERATURE RANGE
IDT72V3664 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
4,096 x 36 x 2
Figure 33. Output Load and AC Test Conditions
NOTE:
1. Includes probe and jig capacitance.
4664 drw 35
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
Ω
3.3V
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
≈3 V
1.5 V
1.5 V
1.5 V
1.5 V
OH
≈O V
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

72V3664L10PF

Mfr. #:
Buy 72V3664L10PF
Manufacturer:
Description:
FIFO BIDIRECTIONAL/ BUS 4KX36X2
Lifecycle:
New from this manufacturer.
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