PCA9501BS,118 Datasheet PCA9501BS,118, PCA9501PW,118, PCA9501D,112 | P10-P12

Product data sheet Rev. 04 — 10 February 2009 10 of 28

NXP Semiconductors

PCA9501

8-bit I

C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM

7.4.2.2 Random read

The PCA9501’s random read mode allows the address to be read from to be speciﬁed by

the master. This is done by performing a dummy write to set the address counter to the

location to be read. The master must perform a byte write to the address location to be

read, but instead of transmitting the data after receiving the acknowledge from the

PCA9501, the master re-issues the START condition and memory slave address with the

R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next

eight clock cycles to transmit the data contained in the addressed location. The master

ceases the transmission by issuing the STOP condition after the eighth bit, omitting the

ninth clock cycle acknowledge.

7.4.2.3 Sequential read

The PCA9501 sequential read is an extension of either the current address read or

random read. If the master does not issue a STOP condition after it has received the

eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the

address counter and use the next eight cycles to transmit the data from that location. The

master can continue this process to read the contents of the entire memory. Upon

reaching address 255 the counter will return to address 0 and continue transmitting data

until a STOP condition is received. The master ceases the transmission by issuing the

STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.

Fig 14. Current address read

1 AS

slave address (memory)

START condition R/W acknowledge

from slave

002aad298

data from memory

SDA A5 A4 A3 A2 A1 A01 P

STOP condition

Fig 15. Random read

0 AS

slave address (memory)

START condition R/W acknowledge

from slave

002aad299

word address

SDA A5 A4 A3 A2 A1 A01 P

STOP

condition

acknowledge

from slave

data from memory

acknowledge

from slave

slave address (memory)

START condition R/W

A5 A4 A3 A2 A1 A01

Fig 16. Sequential read

1 AS

slave address (memory)

START condition R/W acknowledge

from slave

002aad300

data from memory

SDA A5 A4 A3 A2 A1 A01 P

STOP

condition

acknowledge

from master

data from memory

DATA n

data from memory

DATA n + 1 A

acknowledge

from master

DATA n + X

Product data sheet Rev. 04 — 10 February 2009 11 of 28

NXP Semiconductors

PCA9501

8-bit I

C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM

8. Characteristics of the I

C-bus

The I

C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 17).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 18).

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 19).

Fig 17. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 18. Deﬁnition of START and STOP conditions

mba608

SDA

SCL

STOP condition

START condition

Product data sheet Rev. 04 — 10 February 2009 12 of 28

NXP Semiconductors

PCA9501

8-bit I

C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 19. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

C-BUS

MULTIPLEXER

SLAVE

Fig 20. Acknowledgement on the I

C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

PCA9501BS,118

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NXP Semiconductors

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Interface - I/O Expanders 8BIT I2C FMQB GPIONT

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PCA9501BS,118

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