PCA9501_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 February 2009 17 of 28
NXP Semiconductors
PCA9501
8-bit I
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
12. Dynamic characteristics
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
[2] t
pu(R)
and t
pu(W)
are the delays required from the time V
DD
is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
[3] T
cy(W)
is the maximum time that the device requires to perform the internal write operation.
Table 6. Dynamic characteristics
Symbol Parameter Conditions Min Typ Max Unit
I
2
C-bus timing
[1]
(see Figure 24)
f
SCL
SCL clock frequency - - 400 kHz
t
SP
pulse width of spikes that must be
suppressed by the input filter
- - 50 ns
t
BUF
bus free time between a STOP and START
condition
1.3 - - µs
t
SU;STA
set-up time for a repeated START condition 0.6 - - µs
t
HD;STA
hold time (repeated) START condition 0.6 - - µs
t
r
rise time of both SDA and SCL signals - - 0.3 µs
t
f
fall time of both SDA and SCL signals - - 0.3 µs
t
SU;DAT
data set-up time 250 - - ns
t
HD;DAT
data hold time 0 - - ns
t
VD;DAT
data valid time SCL LOW to
data output
- - 1.0 µs
t
SU;STO
set-up time for STOP condition 0.6 - - µs
Port timing
t
v(Q)
data output valid time C
L
≤ 100 pF - - 4 µs
t
su(D)
data input set-up time C
L
≤ 100 pF 0 - - µs
t
h(D)
data input hold time C
L
≤ 100 pF 4 - - µs
Interrupt timing
t
v(INT)
valid time on pin INT C
L
≤ 100 pF - - 4 µs
t
rst(INT)
reset time on pin INT C
L
≤ 100 pF - - 4 µs
Power-up timing
t
pu(R)
read power-up time
[2]
--1ms
t
pu(W)
write power-up time
[2]
--5ms
Write cycle limits (see
Figure 25)
T
cy(W)
write cycle time
[3]
- 5 10 ms
Table 7. Non-volatile storage specifications
Parameter Specification
memory cell data retention 10 years minimum
number of memory cell write cycles 100,000 cycles minimum
