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PCA9501BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
PCA9501_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 February 2009 7 of 28
NXP Semiconductors
PCA9501
8-bit I
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.3.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to V
DD
is active. An additional strong pull-up to V
DD
allows fast rising edges into
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See Figure 9.
7.3.2 Interrupt
The PCA9501 provides an open-drain output (INT) which can be fed to a corresponding
input of the microcontroller. This gives these chips a type of master function which can
initiate an action elsewhere in the system. See Figure 10.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode.
After time t
v(INT)
the signal INT is valid. See Figure 11.
Resetting and reactivating the interrupt circuit is achieved when data on the port is
changed to the original setting or data is read from or written to the port which has
generated the interrupt.
Resetting occurs as follows:
• In the Read mode at the acknowledge bit after the rising edge of the SCL signal
• In the Write mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL
signal
• Returning of the port data to its original setting
• Interrupts which occur during the acknowledge clock pulse may be lost (or very short)
due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting will be detected and, after the next rising clock
edge, will be transmitted as INT. Reading from or writing to another device does not affect
the interrupt circuit.
Fig 9. Transient pull-up current (I
OHt
) while IO3 changes from LOW to HIGH and back to LOW
0 AS
slave address (I/O expander)
START condition R/W acknowledge
from slave
002aad292
1
data to port
A
acknowledge
from slave
12345678SCL 9
SDA 0 A
IO3 output voltage
IO3 pull-up output current
acknowledge
from slave
data to port
A5 A4 A3 A2 A1 A00
IO3
P
STOP
condition
IO3
I
OHt
I
OH
PCA9501_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 February 2009 8 of 28
NXP Semiconductors
PCA9501
8-bit I
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4 Memory operations
7.4.1 Write operations
Write operations require an additional address field to indicate the memory address
location to be written. The address field is eight bits long providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and ‘page
write’.
Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
7.4.1.1 Byte write
To perform a byte write, the START condition is followed by the memory slave address and
the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9501 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
Fig 10. Application of multiple PCA9501s with interrupt
Fig 11. Interrupt generated by a change of input to IO5
002aad293
V
DD
MICROCONTROLLER
INT
PCA9501
INT
PCA9501
INT
device 1 device 2
PCA9501
INT
device 16
1 AS
slave address (I/O expander)
START condition R/W
acknowledge
from slave
002aad294
1
data from port
1
12345678SCL 9
SDA
data into IO5
INT
A5 A4 A3 A2 A1 A00
IO5
P
STOP
condition
t
v(INT)
t
rst(INT)
PCA9501_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 February 2009 9 of 28
NXP Semiconductors
PCA9501
8-bit I
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4.1.2 Page write
A page write is initiated in the same way as the byte write, if after sending the first word of
data the STOP condition is not received, the PCA9501 considers subsequent words as
data. After each data word the PCA9501 responds with an acknowledge and the four least
significant bits of the memory address field are incremented. Should the master not send
a STOP condition after 16 data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
7.4.2 Read operations
PCA9501 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
7.4.2.1 Current address read
The PCA9501 contains an internal address counter that increments after each read or
write access and as a result, if the last word accessed was at address ‘n’ then the address
counter contains the address ‘n + 1’.
When the PCA9501 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address stored in the address counter. The master ceases the transmission by issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
Fig 12. Byte write
0 AS
slave address (memory)
START condition R/W acknowledge
from slave
002aad296
word address
SDA A5 A4 A3 A2 A1 A01 P
STOP condition.
Write to the memory
is performed.
A
acknowledge
from slave
data
A
acknowledge
from slave
Fig 13. Page write
0 AS
slave address (memory)
START condition R/W acknowledge
from slave
002aad297
word address
SDA A5 A4 A3 A2 A1 A01 P
STOP condition.
Write to the memory is performed.
A
acknowledge
from slave
data to memory
A
acknowledge
from slave
DATA n
data to memory
A
acknowledge
from slave
DATA n + 3
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PCA9501BS,118

Mfr. #:
Buy PCA9501BS,118
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders 8BIT I2C FMQB GPIONT
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New from this manufacturer.
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