LTC3765IMSE#TRPBF Datasheet LTC3765EMSE#TRPBF, LTC3765IMSE#TRPBF, LTC3765HMSE#TRPBF | P13-P15

LTC3765

3765fb

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APPLICATIONS INFORMATION

These two equations result in a wide range of values for

NDRV

. For many applications, a 100k resistor will satisfy

these requirements.

The rate of charge of V

from 0V to 8.5V is controlled

by the LTC3765 to be approximately 35µs regardless of

the size of the capacitor connected to the V

pin. The

charging current for this capacitor can be approximated as:

8.5V

35µs

The external NMOS should be chosen so that the I

capacitor charging current in the equation above does

not exceed the safe operating area (SOA) of the NMOS.

Excessive values of C1 are unnecessary and should be

avoided. Typically values in the 1µF to 10µF range work

well. A standard 3V threshold NMOS should be used when

possible to better tolerate a high voltage start-up transient;

however, a logic-level NMOS may be used for applications

that require low voltage start-up. Since the NMOS is on

continuously only during the brief start-up period, a small

SOT-23 package can be used.

If an 8.5V to 14.5V supply is available in the system that

can be used to power V

, the linear regulator is not

needed and should be disabled by tying NDRV to V

The external supply should be connected to the V

through a series diode if the LTC3766 is configured to

overdrive V

when it begins switching.

Low Input Voltage Start-Up

The minimum value of R

NDRV

is further constrained if low

voltage (V

< 10V) start-up is required. In this application,

the previous equation for the maximum value of R

NDRV

must be satisfied to start the charge pump. Additionally,

the charge pump current flows through R

NDRV

to raise the

NDRV voltage above V

so that the external MOSFET can be

fully enhanced. R

NDRV

therefore needs to be large enough

that the limited charge pump current can raise the NDRV

voltage to this level. Lower threshold logic-level MOSFETs

are preferred for low voltage start-up not only because the

MOSFET requires a lower NDRV voltage above V

, but

also because the charge pump current increases as the

NDRV-V

difference decreases, which is approximately

the MOSFET threshold. For a given threshold voltage,

NDRV

should be chosen so that it meets the following

relationship, keeping in mind that the previous equation

for the maximum value of R

NDRV

must also be met.

NDRV

TH(MAX)

5 – V

TH(MAX)













•100k

In this equation, V

is the maximum threshold voltage of

the external MOSFET. Table 1 below shows typical values

of R

NDRV

for common input voltage ranges.

Table 1. Typical R

NDRV

Values

RANGE V

TH(MAX)

NDRV

RANGE TYPICAL R

NDRV

8V to 36V 2V 70k to 180k 125k

36V to 72V 4V 60k to 1.4M 150k

Setting the Overcurrent Limit

The overcurrent limit for the LTC3765 is principally a safety

feature to protect the converter. The current that flows in

series through the transformer primary winding and the

primary switch is sensed by a resistor (R

SENSE

) connected

between the source of the switch and ground. The voltage

across this resistor is sensed by the I

and I

–

pins. If

the difference between I

and I

–

exceeds 150mV, the

LTC3765 immediately turns off the primary NMOS and, if

SSFLT is not grounded, faults. The overcurrent comparator

is blanked for approximately 200ns after PG goes high to

avoid false trips due to noise.

LTC3765

3765fb

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APPLICATIONS INFORMATION

Choose the overcurrent trip current I

TRIP

to be less than

the maximum pulsed drain current rating of the primary

NMOS but greater than the sum of the peak inductor current

at full load and the current required to charge the output

capacitor at start-up, reflected through the transformer.

The sense resistor value, R

SENSE

, can be calculated from

the 150mV trip threshold and the primary-side trip current

from the following equation:

SENSE

150mV

TRIP

The R

SENSE

resistor should be verified to have sufficient

margin over the maximum operating current of the con-

verter, which typically occurs at start-up into a full load.

a self-starting application at full load, the linearly increas-

ing duty

cycle determined by the soft-start capacitor (C

)

ramps the output voltage with a fixed rate independent

of the output capacitor value. Larger output capacitance

requires a proportionally larger charging current to main

tain the output voltage ramp rate. Since additional output

capacitance

is generally distributed through a system and

may not be exactly known, the sense resistor and soft-

start capacitor should be chosen with sufficient margin

to ensure that the overcurrent comparator does not trip

on start-up. An upper bound for the available current to

charge the output capacitor can be calculated as shown

in the following equation:

CHG

150mV

SENSE

•N

– 1.4

LOAD(MAX)

where N

is the turns ratio of the transformer and the

factor of 1.4 accounts for the typical 40% ripple current

in the inductor. To ensure that the overcurrent comparator

does not trip on start-up, the soft-start capacitor should

be chosen so that only a fraction of the charging cur

rent calculated

above is available to charge the output

capacitor. Using 10% of the maximum charging current

generally allows for sufficient margin. This establishes a

lower bound on the soft-start capacitor value, which can

be computed from:

> 600 •10

–9

• V

IN(MAX)

•N

OUT

0.1•I

CHG













where C

OUT

is the output capacitor value and V

IN(MAX)

the maximum input voltage. The soft-start capacitor value

should be in the range of 10nF to 1µF. Do not use a value

less than 10nF. The soft-start capacitor also determines the

relative timing of the output voltage rise and the LTC3766

bias supply rise. The value chosen should be verified with

the equations in the following Self-Starting Start-Up sec

tion to ensure that the bias supply rises before the output

voltage is close to the regulation point.

Care

should be taken with the routing of the I

and I

–

traces to avoid noise pickup. The traces should be Kelvin-

sensed off of the sense resistor and routed right beside

each other on an inner layer of the PCB. Avoid routing near

high voltage, high slew rate nodes such as the drain of the

primary NMOS and the drain of the active clamp PMOS.

Depending on PCB layout and the shielding of the traces

going to the I

and I

–

pins, it is sometimes necessary

to add a small amount of filtering as shown in Figure 5.

Typically,

values of R

= 100Ω and C

= 200pF to 1nF

will provide adequate filtering of noise pickup without

significantly degrading the overcurrent response time.

SENSE

PRIMARY

NMOS

–

LTC3765

3765 F05

Figure 5. Overcurrent Sense Filtering

LTC3765

3765fb

For more information www.linear.com/LTC3765

APPLICATIONS INFORMATION

Self-Starting Start-Up

When starting up, the LTC3765 begins switching in an

open-loop fashion to supply power to the secondary side

LTC3766. When the LTC3766 has adequate bias voltage

and has met other conditions for start-up, it begins sending

both duty cycle information and power through the pulse

transformer connected to the IN

/IN

–

pins.

The LTC3765’s start-up switching frequency is set by a

resistor from FSUV to ground. Since the internal oscilla

tor is only used in start-up, the frequency accuracy is not

critical; however, avoid setting the frequency excessively

low, as this will cause high currents in the transformer and

inductor. To minimize the impact on the transition due to

the duty cycle handoff from the LTC3765 to the LTC3766,

this frequency should be set to the approximately the same

frequency as the LTC3766. The frequency set resistor

) value can be selected using the following equation:

6.2 • 10

– 4.5k

Table 2 shows standard 5% resistor values of R

for

common switching frequencies.

Table 2. Standard R

Resistor Values for Common Frequencies

FREQUENCY R

VALUE

150kHz 36k

200kHz 27k

250kHz 20k

275kHz 18k

350kHz 13k

The internal oscillator generates a ramp that is compared

with the voltage on the SSFLT pin to generate a duty cycle.

The internal oscillator has an offset that prevents switch

ing until SSFLT reaches approximately 1V. When V

undervoltage or the RUN pin is below its threshold, the

SSFLT pin is internally grounded and the drivers therefore

do not switch.

When start-up conditions have been met, the SSFLT pin is

released and a current is sourced out of the pin to charge

an external capacitor connected from SSFLT to ground.

Initially, a 60µA current is sourced out of the pin; how

ever, this current is reduced to approximately 4µA when

begins switching. The 60µA initial current reduces

delay due to charging the external capacitor to 1V, where

switching begins.

During the open-loop start-up, the output voltage rises

much more quickly at high line than at low line for a given

duty cycle ramp rate. This has the potential to overvolt

age the output before the LTC3766 has begun switching,

particularly

at no load. To avoid this situation, the 4µA

soft-start

current is modulated by the RUN pin voltage,

which monitors V

through a resistive divider. When the

RUN pin voltage increases from 1.3V to 3.75V, the soft-

start current decreases from 4µA to 1.6µA.

As the external soft-start capacitor gradually charges

from 1V to 3V, the duty cycle increases linearly from 0%

to 70%. For SSFLT voltages above 3V, the duty cycle is

clamped at approximately 70% to allow for adequate active

clamp reset time. When the SSFLT voltage reaches 3.5V,

if duty cycle information has not been received at the IN

and IN

–

pins, the voltage is held and the linear regulator

is turned off. The PG and AG gate drivers will continue to

switch at 70% duty cycle and the V

supply will decrease

until it reaches its falling undervoltage lockout threshold.

At that point, the LTC3765 will fault, turn on the linear

regulator, and gradually reset the SSFLT capacitor for a

restart attempt.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

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Description:

Switching Voltage Regulators Active Clamp For Cntr & Gate Drvr

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